64Mb: x32
SDRAM
READ – WITHOUT AUTO PRECHARGE 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
t
CMH
CMS
DQM 0-3
A0-A9
t
t
AH
AS
2
ROW
ROW
COLUMN m
t
t
AH
AS
ALL BANKS
ROW
ROW
A10
SINGLE BANK
DISABLE AUTO PRECHARGE
BANK
t
t
AH
AS
BA0, BA1
BANK
BANK
t
BANK
t
t
AC
AC
AC
t
t
t
t
t
OH
AC
OH
OH
OH
DOUT
m
DOUT m + 1
D
OUT m + 2
DOUT m + 3
DQ
t
LZ
t
HZ
t
t
RCD
CAS Latency
RP
t
RAS
t
RC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
MAX
5.5
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
MAX
MIN
MAX UNITS
t
t
AC (3)
4.5
5.5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
CMS
1
1
1
2
ns
ns
t
t
t
t
t
t
AC (2)
-
-
7.5
1.5
1.5
t
AC (1)
17
17
HZ (3)
HZ (2)
HZ (1)
4.5
5.5
7.5
17
5.5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AH
AS
1
1.5
2
1
1.5
2.5
2.5
6
1
2
-
-
t
t
t
17
CH
2.75
2.75
7
LZ
1
1
1
t
CL
2
OH
1.5
2
2.5
42
70
20
20
t
t
CK (3)
CK (2)
CK (1)
5
RAS
RC
38.7 120,000
42
60
18
18
120,000
120,000
t
t
t
t
t
t
-
10
20
1
10
20
1
55
15
15
-
RCD
CKH
1
RP
t
CKS
1.5
1.5
2
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A8 and A9 = “Don’t Care.”
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
42
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