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MT48LC2M32B2TG 参数 Datasheet PDF下载

MT48LC2M32B2TG图片预览
型号: MT48LC2M32B2TG
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM [SYNCHRONOUS DRAM]
分类和应用: 动态存储器
文件页数/大小: 53 页 / 1810 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT48LC2M32B2TG的Datasheet PDF文件第28页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第29页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第30页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第31页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第33页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第34页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第35页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第36页  
64Mb: x32  
SDRAM  
CAPACITANCE  
(Note: 2; notes appear on page 35)  
PARAMETER  
SYMBOL MIN  
MAX UNITS  
Input Capacitance: CLK  
CI1  
CI2  
CIO  
2.5  
2.5  
4.0  
4.0  
4.0  
6.5  
pF  
pF  
pF  
Input Capacitance: All other input-only pins  
Input/Output Capacitance: DQs  
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS  
(Notes: 5, 6, 8, 9, 11; notes appear on page 35)  
AC CHARACTERISTICS  
PARAMETER  
Access time from CLK  
(pos.edge)  
-5  
-55  
SYMBOL  
MIN MAX MIN MAX UNITS NOTES  
t
CL = 3  
CL = 2  
CL = 1  
AC(3)  
AC(2)  
AC(1)  
4.5  
-
-
5
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
ns  
ns  
ns  
t
t
t
Address hold time  
Address setup time  
CLK high-level width  
CLK low-level width  
Clock cycle time  
AH  
AS  
CH  
CL  
1
1.5  
2
2
5
1
1.5  
2
2
5.5  
-
t
t
t
t
CL = 3  
CL = 2  
CL = 1  
CK (3)  
CK (2)  
23  
23  
23  
t
-
t
CK (1)  
-
1
1.5  
1
1.5  
1
1.5  
4.5  
-
-
1
-
1
1.5  
1
1.5  
1
1.5  
5
-
-
1
t
CKE hold time  
CKE setup time  
CS#, RAS#, CAS#, WE#, DQM hold time  
CS#, RAS#, CAS#, WE#, DQM setup time  
Data-in hold time  
CKH  
CKS  
t
t
CMH  
CMS  
t
t
DH  
DS  
t
Data-in setup time  
Data-outhigh-impedancetime  
t
CL = 3  
CL = 2  
CL = 1  
HZ (3)  
HZ (2)  
HZ (1)  
10  
10  
10  
t
t
t
Data-outlow-impedancetime  
Data-outholdtime  
ACTIVE to PRECHARGE command  
ACTIVE to ACTIVE command period  
AUTO REFRESH period  
ACTIVE to READ or WRITE delay  
Refresh period (4,096 rows)  
PRECHARGE command period  
ACTIVE bankatoACTIVEbankbcommand  
Transition time  
LZ  
t
OH  
1.5  
2
t
RAS  
RC  
RFC  
38.7 120k 38.7 120k  
t
55  
60  
15  
55  
60  
t
t
RCD  
16.5  
t
REF  
64  
64  
t
RP  
15  
10  
0.3  
2
16.5  
11  
t
RRD  
25  
7
24  
20  
t
T
1.2  
0.3  
2
55  
1.2  
t
t
WRITE recovery time  
Exit SELF REFRESH to ACTIVE command  
WR  
CK  
ns  
t
XSR  
55  
64Mb: x32 SDRAM  
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02  
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.  
©2002,MicronTechnology,Inc.  
32  
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