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MT48H16M32LFCM-75L 参数 Datasheet PDF下载

MT48H16M32LFCM-75L图片预览
型号: MT48H16M32LFCM-75L
PDF下载: 下载PDF文件 查看货源
内容描述: 512MB :梅格32 ×16 , 16兆×32移动SDRAM [512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM]
分类和应用: 内存集成电路动态存储器时钟
文件页数/大小: 73 页 / 2407 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM  
Op e ra t io n s  
Fig u re 13: Ra n d o m READ Acce sse s  
T0  
T1  
T2  
T3  
T4  
T5  
CLK  
COMMAND  
ADDRESS  
DQ  
READ  
READ  
READ  
READ  
NOP  
NOP  
BANK,  
COL n  
BANK,  
COL a  
BANK,  
COL x  
BANK,  
COL m  
DOUT  
DOUT  
D
OUT  
D
OUT  
n
a
x
m
CL = 2  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
READ  
READ  
READ  
READ  
NOP  
NOP  
NOP  
COMMAND  
ADDRESS  
DQ  
BANK,  
COL n  
BANK,  
COL a  
BANK,  
COL x  
BANK,  
COL m  
DOUT  
D
OUT  
D
OUT  
D
OUT  
n
a
x
m
CL = 3  
DON’T CARE  
Notes: 1. Each READ command may be to any bank. DQM is LOW.  
Data from any READ burst may be truncated with a subsequent WRITE command, and  
data from a fixed-length READ burst may be immediately followed by data from a  
WRITE command (subject to bus turnaround limitations). The WRITE burst may be  
initiated on the clock edge immediately following the last (or last desired) data element  
from the READ burst, provided that I/ O contention can be avoided. In a given system  
design, there may be a possibility that the device driving the input data will go Low-Z  
before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur  
between the last read data and the WRITE command.  
The DQM input is used to avoid I/ O contention, as shown in Figure 14 on page 27 and  
Figure 15 on page 28. The DQM signal must be asserted (HIGH) at least two clocks prior  
to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-  
out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or  
remain High-Z), regardless of the state of the DQM signal, provided the DQM was active  
on the clock just prior to the WRITE command that truncated the READ command. If  
not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during  
T4 (in Figure 15 on page 28) then the WRITEs at T5 and T7 would be valid, while the  
WRITE at T6 would be invalid.  
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03  
MT48H32M16LF_1.fm - Rev. H 6/07 EN  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
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©2005 Micron Technology, Inc. All rights reserved.