512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Op e ra t io n s
WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure 18.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other
commands have been initiated, the DQs will remain High-Z and any additional input
data will be ignored (see Figure 19 on page 31).
Fig u re 18: WRITE Co m m a n d
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
COLUMN
ADDRESS
A0–A8
A9, A11, A12
EN AP
DIS AP
A101
BANK
ADDRESS
BA0, BA1
VALID ADDRESS
DON’T CARE
Notes: 1. EN AP = enable auto precharge
DIS AP = disable auto precharge
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 20 on page 31. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. The 512Mb SDRAM uses a pipe-
lined architecture and therefore does not require the 2n rule associated with a prefetch
architecture. A WRITE command can be initiated on any clock cycle following a previous
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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