512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Op e ra t io n s
Fig u re 9:
Act iva t in g a Sp e cific Ro w in a Sp e cific Ba n k
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
ROW
ADDRESS
A0–A12
BANK
ADDRESS
BA0, BA1
DON´T CARE
t
t
t
Fig u re 10: Exa m p le : Me e t in g RCD (MIN) Wh e n 2 < RCD (MIN)/ CK < 3
T0
T1
T2
T3
CLK
t
t
t
CK
CK
CK
READ or
WRITE
COMMAND
ACTIVE
NOP
NOP
t
RCD (MIN)
DON’T CARE
READs
READ bursts are initiated with a READ command, as shown in Figure 11.
The starting column and bank addresses are provided with the READ command, and
auto precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst. For the
generic READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CL after the READ command. Each subsequent data-out
element will be valid by the next positive clock edge. Figure 12 on page 25 shows general
timing for each possible CL setting.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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