512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Op e ra t io n s
Fig u re 15: READ-t o -WRITE w it h Ext ra Clo ck Cycle
T0
T1
T2
T3
T4
T5
CLK
DQM
READ
NOP
NOP
NOP
NOP
WRITE
COMMAND
ADDRESS
BANK,
COL b
BANK,
COL n
t
HZ
DOUT
n
DIN
b
DQ
t
DS
DON’T CARE
Notes: 1. CL = 3. The READ command may be to any bank, and the WRITE command may be to any
bank.
Fig u re 16: READ-t o -PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
COMMAND
ADDRESS
DQ
X = 1 cycle
BANK
(a or all)
BANK a,
BANK a,
ROW
COL
n
D
OUT
D
n + 1
OUT
DOUT
DOUT
n + 3
n
n + 2
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
COMMAND
ADDRESS
DQ
X = 2 cycles
BANK
(a or all)
BANK a,
BANK a,
ROW
COL
n
D
OUT
DOUT
DOUT
DOUT
n + 3
n
n + 1
n + 2
CL = 3
DON’T CARE
Notes: 1. DQM is LOW.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
28