512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Op e ra t io n s
Fig u re 12: Co n se cu t ive READ Bu rst s
T0
T1
T2
T3
T4
T5
T6
CLK
READ
NOP
NOP
NOP
READ
NOP
NOP
COMMAND
X = 1 cycle
BANK,
COL n
BANK,
COL b
ADDRESS
D
OUT
D
n + 1
OUT
D
n + 2
OUT
D
n + 3
OUT
D
OUT
DQ
n
b
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
COMMAND
X = 2 cycles
BANK,
COL n
BANK,
COL b
ADDRESS
D
OUT
D
n + 1
OUT
D
n + 2
OUT
D
n + 3
OUT
D
OUT
DQ
n
b
CL = 3
DON’T CARE
Notes: 1. Each READ command may be to any bank. DQM is LOW.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
25