1Gb: x4, x8, x16 DDR2 SDRAM
State Diagram
State Diagram
Figure 2: Simplified State Diagram
CKE_L
Initialization
sequence
OCD
default
Self
refreshing
PRE
Idle
all banks
precharged
Setting
MRS
EMRS
(E)MRS
REFRESH
Refreshing
Precharge
power-
down
CKE_L
Automatic Sequence
Command Sequence
ACT
ACT = ACTIVATE
CKE_H = CKE HIGH, exit power-down or self refresh
CKE_L = CKE LOW, enter power-down
(E)MRS = (Extended) mode register set
PRE = PRECHARGE
CKE_L
Activating
PRE_A = PRECHARGE ALL
READ = READ
READ A = READ with auto precharge
REFRESH = REFRESH
Active
power-
down
SR = SELF REFRESH
WRITE = WRITE
WRITE A = WRITE with auto precharge
Bank
active
WRITE
READ
Writing
Reading
READ
WRITE
READ A
WRITE A
Writing
with
auto
Reading
with
auto
PRE, PRE_A
Precharging
precharge
precharge
1. This diagram provides the basic command flow. It is not comprehensive and does not
identify all timing requirements or possible command restrictions such as multibank in-
teraction, power down, entry/exit, etc.
Note:
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2004 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
