1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Table 13: IDD2N and IDD3N Measurement Loop
0
D
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
0
0
0
0
–
–
–
–
1
0
2
D#
D#
3
1
2
3
4
5
6
7
4–7
Repeat sub-loop 0, use BA[2:0] = 1
Repeat sub-loop 0, use BA[2:0] = 2
Repeat sub-loop 0, use BA[2:0] = 3
Repeat sub-loop 0, use BA[2:0] = 4
Repeat sub-loop 0, use BA[2:0] = 5
Repeat sub-loop 0, use BA[2:0] = 6
Repeat sub-loop 0, use BA[2:0] = 7
8–11
12–15
16–19
20–23
24–27
28–31
1. DQ, DQS, DQS# are midlevel.
Notes:
2. DM is LOW.
3. All banks closed during IDD2N; all banks open during IDD3N
.
Table 14: IDD2NT Measurement Loop
0
D
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
0
0
0
0
–
–
–
–
1
0
2
D#
D#
3
1
2
3
4
5
6
7
4–7
Repeat sub-loop 0, use BA[2:0] = 1; ODT = 0
Repeat sub-loop 0, use BA[2:0] = 2; ODT = 1
Repeat sub-loop 0, use BA[2:0] = 3; ODT = 1
Repeat sub-loop 0, use BA[2:0] = 4; ODT = 0
Repeat sub-loop 0, use BA[2:0] = 5; ODT = 0
Repeat sub-loop 0, use BA[2:0] = 6; ODT = 1
Repeat sub-loop 0, use BA[2:0] = 7; ODT = 1
8–11
12–15
16–19
20–23
24–27
28–31
1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.
Notes:
3. All banks closed.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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