1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Table 11: IDD1 Measurement Loop
0
1
2
3
4
ACT
D
0
1
1
1
1
0
0
0
1
1
1
0
0
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
–
–
–
–
D
D#
D#
Repeat cycles 1 through 4 until nRCD - 1; truncate if needed
nRCD
nRAS
RD
0
1
0
1
0
0
0
0
0
0
0
00000000
–
Repeat cycles 1 through 4 until nRAS - 1; truncate if needed
PRE
0
0
1
0
0
0
0
0
0
0
0
Repeat cycles 1 through 4 until nRC - 1; truncate if needed
0
nRC
ACT
D
0
1
1
1
1
0
0
0
1
1
1
0
0
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
F
F
0
0
0
0
0
–
–
–
–
–
nRC + 1
nRC + 2
nRC + 3
nRC + 4
D
D#
D#
Repeat cycles nRC + 1 through nRC + 4 until nRC + nRCD - 1; truncate if needed
RD 00110011
Repeat cycles nRC + 1 through nRC + 4 until nRC + nRAS - 1; truncate if needed
PRE
nRC + nRCD
nRC + nRAS
0
1
0
1
0
0
0
0
0
F
0
0
0
1
0
0
0
0
0
0
F
0
–
Repeat cycle nRC + 1 through nRC + 4 until 2 × nRC - 1; truncate if needed
Repeat sub-loop 0, use BA[2:0] = 1
1
2
3
4
5
6
7
2 × nRC
4 × nRC
6 × nRC
8 × nRC
10 × nRC
12 × nRC
14 × nRC
Repeat sub-loop 0, use BA[2:0] = 2
Repeat sub-loop 0, use BA[2:0] = 3
Repeat sub-loop 0, use BA[2:0] = 4
Repeat sub-loop 0, use BA[2:0] = 5
Repeat sub-loop 0, use BA[2:0] = 6
Repeat sub-loop 0, use BA[2:0] = 7
1. DQ, DQS, DQS# are midlevel unless driven as required by the RD command.
2. DM is LOW.
Notes:
3. Burst sequence is driven on each DQ signal by the RD command.
4. Only selected bank (single) active.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
36
2006 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
