1Gb: x4, x8, x16 DDR3 SDRAM
Write Leveling
When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQ
outputs the sampled CK’s status. The prime DQ for a x4 or x8 configuration is DQ± with
all other DQ (DQ[0:1]) driving LOW. The prime DQ for a x16 configuration is DQ± for the
lower byte and DQ8 for the upper byte. It outputs the status of CK sampled by LDQS
and UDQS. All other DQ (DQ[0:1], DQ[15:9]) continue to drive LOW. Two prime DQ on a
x16 enable each byte lane to be leveled independently.
The write leveling mode register interacts with other mode registers to correctly config-
ure the write leveling functionality. Besides using MR1[0] to disable/enable write level-
ing, MR1[12] must be used to enable/disable the output buffers. The ODT value, burst
length, and so forth need to be selected as well. This interaction is shown in Table 05. It
should also be noted that when the outputs are enabled during write leveling mode, the
DQS buffers are set as inputs, and the DQ are set as outputs. Additionally, during write
leveling mode, only the DQS strobe terminations are activated and deactivated via the
ODT ball. The DQ remain disabled and are not affected by the ODT ball.
Table 75: Write Leveling Matrix
Note 1 applies to the entire table
DRAM
RTT,nom
MR1[7]
MR1[12] MR1[2, 6, 9]
Write
Leveling
Output
Buffers
RTT,nom
Value
DRAM
ODT Ball DQS DQ
DRAM State
Case Notes
Disabled
See normal operations
Write leveling not enabled
0
Enabled
(1)
Disabled
(1)
n/a
Low
High
Low
High
Off
On
Off
On
Off DQS not receiving: not terminated
Prime DQ High-Z: not terminated
Other DQ High-Z: not terminated
1
2
3
4
2
ꢃꢄΩꢎꢋꢇꢄΩꢎ
ꢆꢄΩꢎꢋꢅꢄΩ, or
120Ω
DQS not receiving: terminated by RTT
Prime DQ High-Z: not terminated
Other DQ High-Z: not terminated
Enabled
(0)
n/a
DQS receiving: not terminated
Prime DQ driving CK state: not terminated
Other DQ driving LOW: not terminated
3
ꢆꢄΩꢎꢋꢅꢄΩ, or
120Ω
DQS receiving: terminated by RTT
Prime DQ driving CK state: not terminated
Other DQ driving LOW: not terminated
1. Expected usage if used during write leveling: Case 1 may be used when DRAM are on a
dual-rank module and on the rank not being leveled or on any rank of a module not
being leveled on a multislot system. Case 2 may be used when DRAM are on any rank of
a module not being leveled on a multislot system. Case 3 is generally not used. Case 4 is
generally used when DRAM are on the rank that is being leveled.
Notes:
2. Since the DRAM DQS is not being driven (MR1[12] = 1), DQS ignores the input strobe,
and all RTT,nom values are allowed. This simulates a normal standby state to DQS.
3. Since the DRAM DQS is being driven (MR1[12] = 0), DQS captures the input strobe, and
only some RTT,nom values are allowed. This simulates a normal write state to DQS.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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