1Gb: x4, x8, x16 DDR3 SDRAM
Write Leveling
Figure 48: Write Leveling Sequence
T1
T2
tWLH
NOP
tWLS
CK#
CK
MRS1
NOP2
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
tMOD
ODT
t
tDQSL3
tDQSH3
3
tWLDQSEN
tDQSL3
DQSH
Differential DQS4
Prime DQ5
tWLMRD
tWLO
tWLO
tWLO
t
WLOE
Early remaining DQ
Late remaining DQ
tWLO
Indicates break
in time scale
Undefined Driving Mode
Don’t Care
1. MRS: Load MR1 to enter write leveling mode.
2. NOP: NOP or DES.
Notes:
3. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH (MIN) and tDQSL
(MIN) as defined for regular writes. The maximum pulse width is system-dependent.
4. Differential DQS is the differential data strobe (DQS, DQS#). Timing reference points are
the zero crossings. The solid line represents DQS; the dotted line represents DQS#.
5. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ
are driven LOW and remain in this state throughout the leveling procedure.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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