1Gb: x4, x8, x16 DDR3 SDRAM
State Diagram
State Diagram
Figure 2: Simplified State Diagram
CKE L
Power
applied
MRS, MPR,
write
leveling
Initial-
ization
Power
on
Reset
procedure
Self
refresh
SRE
SRX
ZQCL
MRS
From any
state
RESET
REF
ZQCL/ZQCS
ZQ
calibration
Refreshing
Idle
PDE
ACT
PDX
Active
power-
down
Precharge
power-
down
Activating
PDX
PDE
CKE L
CKE L
Bank
active
WRITE
READ
WRITE
READ
WRITE AP
WRITE
READ AP
READ
Writing
Reading
WRITE AP
READ AP
WRITE AP
READ AP
PRE, PREA
Writing
Reading
PRE, PREA
PRE, PREA
Precharging
Automatic
sequence
Command
sequence
ACT = ACTIVATE
PREA = PRECHARGE ALL
READ = RD, RDS4, RDS8
READ AP = RDAP, RDAPS4, RDAPS8
REF = REFRESH
RESET = START RESET PROCEDURE
SRE = Self refresh entry
SRX = Self refresh exit
WRITE = WR, WRS4, WRS8
WRITE AP = WRAP, WRAPS4, WRAPS8
ZQCL = ZQ LONG CALIBRATION
ZQCS = ZQ SHORT CALIBRATION
MPR = Multipurpose register
MRS = Mode register set
PDE = Power-down entry
PDX = Power-down exit
PRE = PRECHARGE
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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11
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