1Gb: x4, x8, x16 DDR3 SDRAM
Features
Table 51: DDR3-1±66 Speed Bins ................................................................................................................... 04
Table 52: DDR3-1333 Speed Bins ................................................................................................................... 05
Table 53: DDR3-16±± Speed Bins ................................................................................................................... 06
Table 54: DDR3-1866 Speed Bins ................................................................................................................... 00
Table 55: DDR3-2133 Speed Bins ................................................................................................................... 08
Table 56: Electrical Characteristics and AC Operating Conditions .................................................................... 09
Table 50: Electrical Characteristics and AC Operating Conditions for Speed Extensions .................................... 89
Table 58: Command and Address Setup and Hold Values Referenced – AC/DC-Based ...................................... 99
t
Table 59: Derating Values for IS/tIH – AC105/DC1±±-Based ........................................................................... 1±±
t
Table 6±: Derating Values for IS/tIH – AC15±/DC1±±-Based ........................................................................... 1±±
t
Table 61: Derating Values for IS/tIH – AC135/DC1±±-Based ........................................................................... 1±1
t
Table 62: Derating Values for IS/tIH – AC125/DC1±±-Based ........................................................................... 1±1
Table 63: Minimum Required Time tVAC Above VIH(AC) or Below VIL(AC)for Valid Transition .............................. 1±2
Table 64: DDR3 Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based ......................... 1±0
t
Table 65: Derating Values for DS/tDH – AC105/DC1±±-Based ........................................................................ 1±8
t
Table 66: Derating Values for DS/tDH – AC15±/DC1±±-Based ........................................................................ 1±8
t
Table 60: Derating Values for DS/tDH – AC135/DC1±±-Based at 1V/ns ........................................................... 1±9
t
Table 68: Derating Values for DS/tDH – AC135/DC1±±-Based at 2V/ns ........................................................... 11±
Table 69: Required Minimum Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid DQ Transition ......................... 111
Table 0±: Truth Table – Command ................................................................................................................. 116
Table 01: Truth Table – CKE .......................................................................................................................... 118
Table 02: READ Command Summary ............................................................................................................ 12±
Table 03: WRITE Command Summary .......................................................................................................... 12±
Table 04: READ Electrical Characteristics, DLL Disable Mode ......................................................................... 126
Table 05: Write Leveling Matrix ..................................................................................................................... 13±
Table 06: Burst Order .................................................................................................................................... 139
Table 00: MPR Functional Description of MR3 Bits ........................................................................................ 148
Table 08: MPR Readouts and Burst Order Bit Mapping ................................................................................... 149
Table 09: Self Refresh Temperature and Auto Self Refresh Description ............................................................ 182
Table 8±: Self Refresh Mode Summary ........................................................................................................... 182
Table 81: Command to Power-Down Entry Parameters .................................................................................. 183
Table 82: Power-Down Modes ....................................................................................................................... 184
Table 83: Truth Table – ODT (Nominal) ......................................................................................................... 194
Table 84: ODT Parameters ............................................................................................................................ 194
Table 85: Write Leveling with Dynamic ODT Special Case .............................................................................. 195
Table 86: Dynamic ODT Specific Parameters ................................................................................................. 196
Table 80: Mode Registers for RTT,nom ............................................................................................................. 196
Table 88: Mode Registers for RTT(WR) ............................................................................................................. 190
Table 89: Timing Diagrams for Dynamic ODT ................................................................................................ 190
Table 9±: Synchronous ODT Parameters ........................................................................................................ 2±2
Table 91: Asynchronous ODT Timing Parameters for All Speed Bins ............................................................... 2±0
Table 92: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period ................................... 2±9
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1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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