1Gb: x4, x8, x16 DDR3 SDRAM
Functional Block Diagrams
Functional Block Diagrams
DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 8-bank DRAM.
Figure 3: 256 Meg x 4 Functional Block Diagram
ODT
control
ODT
ZQ
To pull-up/pull-down
networks
ZQ CAL
RESET#
CKE
RZQ
ZQCL, ZQCS
Control
logic
V
SSQ
A12
CK, CK#
CS#
VDDQ/2
BC4 (burst chop)
RTT,nom
RTT(WR)
sw2
Columns 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
RAS#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
CK, CK#
DLL
OTF
sw1
CAS#
WE#
(1 . . . 4)
Refresh
14
READ
FIFO
and
data
MUX
counter
Mode registers
16
Bank 0
memory
array
Bank 0
32
Row-
address
MUX
4
14
DQ[3:0]
row-
address
latch
READ
drivers
16,384
DQ[3:0]
(16,384 x 256 x 32)
DQS, DQS#
14
and
decoder
VDDQ/2
Sense amplifiers
8,192
32
BC4
RTT,nom
RTT(WR)
sw2
BC4
OTF
sw1
I/O gating
DM mask logic
3
DM
DQS, DQS#
(1, 2)
Bank
control
logic
A[13:0]
BA[2:0]
Address
register
17
3
V
DDQ/2
256
(x32)
WRITE
drivers
and
input
logic
4
32
RTT,nom
RTT(WR)
sw2
Data
interface
Data
Column
decoder
sw1
Column-
address
counter/
latch
8
3
DM
11
Columns 0, 1, and 2
Column 2
(select upper or
CK, CK#
lower nibble for BC4)
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
14
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