1Gb: x4, x8, x16 DDR3 SDRAM
Features
Figure 51: MRS to MRS Command Timing (tMRD) ......................................................................................... 136
Figure 52: MRS to nonMRS Command Timing (tMOD) .................................................................................. 130
Figure 53: Mode Register ± (MR±) Definitions ................................................................................................ 138
Figure 54: READ Latency .............................................................................................................................. 14±
Figure 55: Mode Register 1 (MR1) Definition ................................................................................................. 141
Figure 56: READ Latency (AL = 5, CL = 6) ....................................................................................................... 144
Figure 50: Mode Register 2 (MR2) Definition ................................................................................................. 145
Figure 58: CAS Write Latency ........................................................................................................................ 145
Figure 59: Mode Register 3 (MR3) Definition ................................................................................................. 140
Figure 6±: Multipurpose Register (MPR) Block Diagram ................................................................................. 148
Figure 61: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 151
Figure 62: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 152
Figure 63: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble .................................... 153
Figure 64: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble .................................... 154
Figure 65: ZQ CALIBRATION Timing (ZQCL and ZQCS) ................................................................................. 156
Figure 66: Example: Meeting tRRD (MIN) and tRCD (MIN) ............................................................................. 150
Figure 60: Example: tFAW ............................................................................................................................. 158
Figure 68: READ Latency .............................................................................................................................. 159
Figure 69: Consecutive READ Bursts (BL8) .................................................................................................... 161
Figure 0±: Consecutive READ Bursts (BC4) .................................................................................................... 161
Figure 01: Nonconsecutive READ Bursts ....................................................................................................... 162
Figure 02: READ (BL8) to WRITE (BL8) .......................................................................................................... 162
Figure 03: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 163
Figure 04: READ to PRECHARGE (BL8) .......................................................................................................... 163
Figure 05: READ to PRECHARGE (BC4) ......................................................................................................... 164
Figure 06: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 164
Figure 00: READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 164
Figure 08: Data Output Timing – tDQSQ and Data Valid Window .................................................................... 166
Figure 09: Data Strobe Timing – READs ......................................................................................................... 160
Figure 8±: Method for Calculating tLZ and tHZ ............................................................................................... 168
Figure 81: tRPRE Timing ............................................................................................................................... 168
Figure 82: tRPST Timing ............................................................................................................................... 169
Figure 83: tWPRE Timing .............................................................................................................................. 101
Figure 84: tWPST Timing .............................................................................................................................. 101
Figure 85: WRITE Burst ................................................................................................................................ 102
Figure 86: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 103
Figure 80: Consecutive WRITE (BC4) to WRITE (BC4) via OTF ........................................................................ 103
Figure 88: Nonconsecutive WRITE to WRITE ................................................................................................. 104
Figure 89: WRITE (BL8) to READ (BL8) .......................................................................................................... 104
Figure 9±: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 105
Figure 91: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 106
Figure 92: WRITE (BL8) to PRECHARGE ........................................................................................................ 100
Figure 93: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 100
Figure 94: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 108
Figure 95: Data Input Timing ........................................................................................................................ 109
Figure 96: Self Refresh Entry/Exit Timing ...................................................................................................... 181
Figure 90: Active Power-Down Entry and Exit ................................................................................................ 185
Figure 98: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 186
Figure 99: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ................................................................ 186
Figure 1±±: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ........................................... 180
Figure 1±1: Power-Down Entry After WRITE .................................................................................................. 180
Figure 1±2: Power-Down Entry After WRITE with Auto Precharge (WRAP) ...................................................... 188
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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