1Gb: x4, x8, x16 DDR3 SDRAM
Features
Figure 1±3: REFRESH to Power-Down Entry .................................................................................................. 188
Figure 1±4: ACTIVATE to Power-Down Entry ................................................................................................. 189
Figure 1±5: PRECHARGE to Power-Down Entry ............................................................................................. 189
Figure 1±6: MRS Command to Power-Down Entry ......................................................................................... 19±
Figure 1±0: Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 19±
Figure 1±8: RESET Sequence ......................................................................................................................... 192
Figure 1±9: On-Die Termination ................................................................................................................... 193
Figure 11±: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 198
Figure 111: Dynamic ODT: Without WRITE Command .................................................................................. 198
Figure 112: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 199
Figure 113: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 2±±
Figure 114: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 2±±
Figure 115: Synchronous ODT ...................................................................................................................... 2±2
Figure 116: Synchronous ODT (BC4) ............................................................................................................. 2±3
Figure 110: ODT During READs .................................................................................................................... 2±5
Figure 118: Asynchronous ODT Timing with Fast ODT Transition .................................................................. 2±0
Figure 119: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ............ 2±9
Figure 12±: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit ............... 211
Figure 121: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 213
Figure 122: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 213
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
10
2006 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
