1Gb: x4, x8, x16 DDR3 SDRAM
Functional Block Diagrams
Figure 4: 128 Meg x 8 Functional Block Diagram
ODT
control
ODT
ZQ
To ODT/output drivers
ZQ CAL
RESET#
CKE
RZQ
Control
logic
ZQCL, ZQCS
VSSQ
A12
CK, CK#
CS#
V
/2
DDQ
BC4 (burst chop)
R
R
TT,nom
TT(WR)
Columns 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
RAS#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
CK, CK#
DLL
OTF
sw2
sw1
CAS#
WE#
(1 . . . 8)
Refresh
counter
DQ8
14
READ
FIFO
and
data
MUX
TDQS#
Mode registers
16
Bank 0
memory
array
Bank 0
Row-
address
MUX
8
14
64
DQ[7:0]
row-
address
latch
READ
drivers
16,384
DQ[7:0]
(16,384 x 128 x 64)
DQS, DQS#
14
and
decoder
V
/2
DDQ
Sense amplifiers
8,192
64
BC4
R
R
TT,nom
TT(WR)
BC4
OTF
sw2
sw1
I/O gating
DM mask logic
3
DQS, DQS#
(1, 2)
Bank
control
logic
A[13:0]
BA[2:0]
Address
register
17
3
V
/2
DDQ
(128
x64)
WRITE
drivers
and
input
logic
8
64
R
R
Data
interface
TT,nom
TT(WR)
Data
sw2
Column
decoder
sw1
Column-
address
counter/
latch
7
3
DM/TDQS
(shared pin)
10
Columns 0, 1, and 2
CK, CK#
Column 2
(select upper or
lower nibble for BC4)
Figure 5: 64 Meg x 16 Functional Block Diagram
ODT
control
ODT
ZQ
ZQ CAL
To ODT/output drivers
RESET#
CKE
RZQ
Control
logic
ZQCL, ZQCS
V
SSQ
A12
CK, CK#
CS#
V
/2
DDQ
BC4 (burst chop)
R
R
TT,nom
TT(WR)
Column 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
RAS#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
CK, CK#
OTF
sw2
sw1
CAS#
WE#
DLL
(1 . . . 16)
Refresh
counter
13
READ
FIFO
and
data
MUX
Mode registers
16
Bank 0
memory
array
Bank 0
row-
Row-
address
MUX
16
13
128
DQ[15:0]
LDQS, LDQS#, UDQS, UDQS#
READ
drivers
address
latch
DQ[15:0]
8,192
(8192 x 128 x 128)
13
and
decoder
V
/2
DDQ
Sense amplifiers
16,384
BC4
128
R
TT,nom
R
TT(WR)
sw2
BC4
OTF
sw1
LDQS, LDQS#
UDQS, UDQS#
I/O gating
DM mask logic
3
Bank
control
logic
(1 . . . 4)
A[12:0]
BA[2:0]
Address
register
16
3
V
/2
DDQ
(128
x128)
WRITE
drivers
and
input
logic
128
16
Data
R
Data
interface
R
TT,nom
TT(WR)
sw2
Column
decoder
sw1
Column-
address
counter/
latch
7
3
LDM/UDM
10
(1, 2)
Columns 0, 1, and 2
Column 2
(select upper or
CK, CK#
lower nibble for BC4)
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
15
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