1Gb: x4, x8, x16 DDR3 SDRAM
Features
List of Figures
Figure 1: DDR3 Part Numbers .......................................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................. 11
Figure 3: 256 Meg x 4 Functional Block Diagram ............................................................................................. 14
Figure 4: 128 Meg x 8 Functional Block Diagram ............................................................................................. 15
Figure 5: 64 Meg x 16 Functional Block Diagram ............................................................................................. 15
Figure 6: 08-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 16
Figure 0: 86-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 10
Figure 8: 96-Ball FBGA – x16 (Top View) ......................................................................................................... 18
Figure 9: 08-Ball FBGA – x4, x8 (JP) ................................................................................................................ 25
Figure 1±: 08-Ball FBGA – x4, x8 (HX) ............................................................................................................. 26
Figure 11: 86-Ball FBGA – x4, x8 (BY) .............................................................................................................. 20
Figure 12: 96-Ball FBGA – x16 (LA) ................................................................................................................. 28
Figure 13: 96-Ball FBGA – x16 (JT) .................................................................................................................. 29
Figure 14: Thermal Measurement Point ......................................................................................................... 33
Figure 15: Input Signal .................................................................................................................................. 49
Figure 16: Overshoot ..................................................................................................................................... 5±
Figure 10: Undershoot ................................................................................................................................... 5±
Figure 18: VIX for Differential Signals .............................................................................................................. 52
Figure 19: Single-Ended Requirements for Differential Signals ........................................................................ 52
Figure 2±: Definition of Differential AC-Swing and tDVAC ............................................................................... 53
Figure 21: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 55
Figure 22: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .................................. 56
Figure 23: ODT Levels and I-V Characteristics ................................................................................................ 50
Figure 24: ODT Timing Reference Load .......................................................................................................... 6±
Figure 25: tAON and tAOF Definitions ............................................................................................................ 61
Figure 26: tAONPD and tAOFPD Definitions ................................................................................................... 61
Figure 20: tADC Definition ............................................................................................................................. 62
Figure 28: Output Driver ................................................................................................................................ 63
Figure 29: DQ Output Signal .......................................................................................................................... 0±
Figure 3±: Differential Output Signal .............................................................................................................. 01
Figure 31: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 01
Figure 32: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 02
Figure 33: Nominal Differential Output Slew Rate Definition for DQS, DQS# .................................................... 03
Figure 34: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) ............................................. 1±3
Figure 35: Nominal Slew Rate for tIH (Command and Address – Clock) ........................................................... 1±4
Figure 36: Tangent Line for tIS (Command and Address – Clock) .................................................................... 1±5
Figure 30: Tangent Line for tIH (Command and Address – Clock) .................................................................... 1±6
Figure 38: Nominal Slew Rate and tVAC for tDS (DQ – Strobe) ......................................................................... 112
Figure 39: Nominal Slew Rate for tDH (DQ – Strobe) ...................................................................................... 113
Figure 4±: Tangent Line for tDS (DQ – Strobe) ................................................................................................ 114
Figure 41: Tangent Line for tDH (DQ – Strobe) ............................................................................................... 115
Figure 42: Refresh Mode ............................................................................................................................... 122
Figure 43: DLL Enable Mode to DLL Disable Mode ........................................................................................ 124
Figure 44: DLL Disable Mode to DLL Enable Mode ........................................................................................ 125
Figure 45: DLL Disable tDQSCK .................................................................................................................... 126
Figure 46: Change Frequency During Precharge Power-Down ........................................................................ 128
Figure 40: Write Leveling Concept ................................................................................................................. 129
Figure 48: Write Leveling Sequence ............................................................................................................... 132
Figure 49: Write Leveling Exit Procedure ....................................................................................................... 133
Figure 5±: Initialization Sequence ................................................................................................................. 135
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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