8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EDO-PAGE-MODEREAD-WRITECYCLE
(LATEWRITEandREAD-MODIFY-WRITEcycles)
t
t
RP
RASP
V
V
IH
IL
RAS#
CAS#
t
t
t
RSH
t
NOTE 1
CSH
PC
PRWC
t
t
t
t
t
t
t
t
CP
CRP
RCD
CAS
CP
CAS
CP
CAS
V
V
IH
IL
t
AR
t
RAD
t
t
t
t
t
t
t
t
CAH
ASR
RAH
ASC
CAH
ASC
CAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
COLUMN
COLUMN
ROW
t
RWD
t
RWL
t
RCS
t
t
CWL
t
CWL
CWL
t
t
t
WP
WP
AWD
WP
AWD
t
t
t
AWD
t
t
t
CWD
CWD
CWD
V
V
IH
IL
WE#
t
AA
t
t
AA
AA
t
RAC
t
DH
t
DH
t
DH
t
t
CPA
CPA
t
CAC
t
t
t
DS
DS
DS
t
t
CAC
CAC
t
t
t
CLZ
CLZ
OPEN
CLZ
V
V
IOH
IOL
VALID
OUT
VALID
IN
VALID
OUT
VALID
IN
VALID
OUT
VALID
IN
DQ
OPEN
D
D
D
D
D
D
t
t
t
OD
OD
OD
t
t
t
OE
t
OE
OE
OEH
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
SYMBOL
MIN
MAX
12
MIN
MAX
15
UNITS
ns
t
t
AA
25
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OD
0
0
t
t
AR
38
0
45
0
OE
12
15
ns
t
t
ASC
OEH
8
10
25
56
ns
t
t
ASR
0
0
PC
20
47
ns
t
t
AWD
42
49
PRWC
ns
t
t
CAC
13
15
RAC
50
60
ns
t
t
CAH
8
8
0
8
10
10
0
RAD
9
9
12
10
60
14
0
ns
t
t
CAS
10,000
10,000
RAH
ns
t
t
CLZ
RASP
50
11
0
125,000
125,000
ns
t
t
CP
10
RCD
ns
t
t
CPA
28
35
RCS
ns
t
t
CRP
5
38
30
8
5
RP
30
13
67
13
5
40
15
79
15
5
ns
t
t
CSH
45
35
10
10
0
RSH
ns
t
t
CWD
RWD
ns
t
t
CWL
RWL
ns
t
t
DH
8
WP
ns
t
DS
0
t
NOTE: 1. PC is for LATE WRITE cycles only.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
20
MICRON [ MICRON TECHNOLOGY ]
