8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
RAS#-ONLY REFRESH CYCLE
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS#
CAS#
t
t
RPC
CRP
V
V
IH
IL
t
t
RAH
ASR
V
V
IH
IL
ADDR
ROW
ROW
V
V
OH
OL
DQ
OPEN
V
V
IH
IL
WE#
CBR REFRESH CYCLE
(Addresses, OE# = DON’T CARE)
t
t
t
t
RAS
RP
RAS
NOTE 1
RP
V
V
IH
IL
RAS#
t
RPC
t
t
t
t
t
t
CHR
RPC
CP
CSR
CHR
CSR
V
V
IH
IL
CAS#
DQ
V
V
OH
OL
OPEN
t
t
t
WRP
t
WRH
WRP
WRH
V
V
IH
IL
WE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
0
MAX
UNITS
ns
SYMBOL
MIN
50
84
30
5
MAX
MIN
60
MAX
10,000
UNITS
ns
t
t
ASR
0
8
8
5
5
9
RAS
10,000
t
t
CHR
10
10
5
ns
RC
104
40
ns
t
t
CP
ns
RP
ns
t
t
CRP
ns
RPC
5
ns
t
t
CSR
5
ns
WRH
8
10
ns
t
t
RAH
10
ns
WRP
8
10
ns
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
23
MICRON [ MICRON TECHNOLOGY ]
