8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EDO READ CYCLE
(withWE#-controlleddisable)
V
V
IH
IL
RAS#
CAS#
t
CSH
t
t
CAS
t
t
CP
RCD
CRP
V
V
IH
IL
t
AR
t
RAD
t
t
t
t
t
ASC
ASR
RAH
ASC
CAH
V
V
IH
IL
ROW
COLUMN
COLUMN
ADDR
WE#
t
RCS
t
t
t
RCH
WPZ
RCS
V
V
IH
IL
t
AA
t
RAC
t
CAC
t
WHZ
t
t
CLZ
CLZ
V
V
OH
OL
DQ
OPEN
OPEN
VALID DATA
t
OE
t
OD
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
SYMBOL
MIN
MAX
12
MIN
MAX
15
UNITS
t
t
AA
25
30
OD
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
AR
38
0
45
0
ns
OE
12
15
t
t
ASC
ns
RAC
50
60
t
t
ASR
0
0
ns
RAD
9
9
12
10
14
0
t
t
CAC
13
15
ns
RAH
t
t
CAH
8
8
10
10
0
ns
RCD
11
0
t
t
CAS
10,000
10,000
ns
RCH
t
t
CLZ
0
ns
RCS
0
0
t
t
CP
8
10
5
ns
WHZ
12
15
t
t
CRP
5
ns
WPZ
10
10
t
CSH
38
45
ns
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
22
MICRON [ MICRON TECHNOLOGY ]
