8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EDO-PAGE-MODE READ EARLY WRITE CYCLE
(PseudoREAD-MODIFY-WRITE)
t
t
RP
RASP
V
V
IH
IL
RAS#
CAS#
t
CSH
t
t
t
PC
RSH
PC
t
t
t
t
t
t
t
t
CP
CRP
RCD
CAS
CP
CAS
CP
CAS
V
V
IH
IL
t
AR
t
t
t
RAD
ACH
CAH
t
t
t
t
t
t
t
ASC
ASR
RAH
ASC
CAH
ASC
CAH
V
V
IH
IL
ADDR
WE#
ROW
COLUMN (A)
COLUMN (B)
ROW
COLUMN (N)
t
t
RCH
t
t
RCS
WCS
WCH
V
V
IH
IL
t
AA
t
AA
t
CPA
t
RAC
t
t
t
DH
t
CAC
DS
CAC
t
t
WHZ
COH
V
V
IOH
IOL
VALID
DATA (B)
DQ
VALID DATA
IN
OPEN
VALID DATA (A)
t
OE
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
t
t
AA
25
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OE
12
15
t
t
ACH
12
38
0
15
45
0
PC
20
25
ns
t
t
AR
RAC
50
60
ns
t
t
ASC
RAD
9
9
12
10
60
14
0
ns
t
t
ASR
0
0
RAH
ns
t
t
CAC
13
15
RASP
50
11
0
125,000
125,000
ns
t
t
CAH
8
8
3
8
10
10
3
RCD
ns
t
t
CAS
10,000
10,000
35
RCH
ns
t
t
COH
RCS
0
0
ns
t
t
CP
10
RP
30
13
8
40
15
10
0
ns
t
t
CPA
28
RSH
ns
t
t
CRP
5
38
8
5
45
10
0
WCH
ns
t
t
CSH
WCS
0
ns
t
t
DH
WHZ
12
15
ns
t
DS
0
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
21