8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
READ-WRITE CYCLE
(LATEWRITEandREAD-MODIFY-WRITEcycles)
t
RWC
t
t
RP
RAS
V
V
IH
IL
RAS#
CAS#
t
CSH
t
RSH
t
t
t
t
CAS
CRP
ASR
RCD
V
V
IH
IL
t
AR
t
t
t
t
t
CAH
RAD
RAH
ASC
RCS
t
ACH
V
V
IH
IL
ADDR
ROW
COLUMN
ROW
t
t
t
t
RWD
CWL
RWL
WP
t
CWD
t
AWD
V
V
IH
IL
WE#
t
AA
t
RAC
t
CAC
t
t
DS
DH
t
CLZ
V
V
IOH
IOL
VALID D
VALID D
DQ
OPEN
OPEN
OUT
IN
t
t
t
OE
OD
OEH
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
SYMBOL
MIN
MAX
12
MIN
MAX
15
UNITS
ns
t
t
AA
25
30
OD
0
0
t
t
ACH
12
38
0
15
45
0
ns
OE
12
15
ns
t
t
AR
ns
OEH
8
10
ns
t
t
ASC
ns
RAC
50
60
ns
t
t
ASR
0
0
ns
RAD
9
9
12
10
60
14
0
ns
t
t
AWD
42
49
ns
RAH
ns
t
t
CAC
13
15
ns
RAS
50
11
0
10,000
10,000
ns
t
t
CAH
8
8
10
10
0
ns
RCD
ns
t
t
CAS
10,000
10,000
ns
RCS
ns
t
t
CLZ
0
ns
RP
30
13
116
67
13
5
40
15
140
79
15
5
ns
t
t
CRP
5
5
ns
RSH
ns
t
t
CSH
38
30
8
45
35
10
10
0
ns
RWC
ns
t
t
CWD
ns
RWD
ns
t
t
CWL
ns
RWL
ns
t
t
DH
8
ns
WP
ns
t
DS
0
ns
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
19
MICRON [ MICRON TECHNOLOGY ]
