8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
20
HIDDEN REFRESH CYCLE
(WE# = HIGH; OE# = LOW)
t
RC
t
t
t
RAS
RAS
RP
V
V
IH
IL
RAS#
CAS#
t
t
t
t
CHR
RSH
CRP
RCD
V
V
IH
IL
t
AR
t
RAD
t
t
t
t
CAH
ASR
RAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
t
AA
t
RAC
t
OFF
t
CAC
t
CLZ
V
V
IOH
IOL
DQ
OPEN
VALID DATA
OPEN
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
t
t
t
t
t
t
t
t
t
t
AA
25
30
OFF
ORD
RAC
RAD
RAH
RAS
RC
0
0
12
0
0
15
t
AR
38
0
45
0
ns
ns
t
ASC
ns
50
60
ns
t
ASR
0
0
ns
9
12
10
ns
t
CAC
13
15
ns
9
ns
t
CAH
8
8
0
5
0
10
10
0
ns
50
84
11
30
13
10,000
60
10,000
ns
t
CHR
ns
104
14
ns
t
CLZ
ns
RCD
ns
t
CRP
5
ns
RP
40
ns
t
t
OD
12
12
0
15
15
ns
RSH
15
ns
t
OE
ns
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
24
MICRON [ MICRON TECHNOLOGY ]
