8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
READ CYCLE
t
RC
t
t
RAS
RP
V
V
IH
IL
RAS#
CAS#
t
CSH
t
t
RSH
RRH
t
t
CAS
t
RCD
CRP
V
V
IH
IL
t
AR
t
t
t
CAH
RAD
ASC
t
t
RAH
t
ASR
ACH
V
V
IH
IL
ROW
ROW
COLUMN
ADDR
WE#
t
t
RCS
RCH
V
V
IH
IL
t
AA
t
RAC
NOTE 1
t
t
CAC
OFF
t
CLZ
V
V
OH
OL
DQ
OPEN
OPEN
VALID DATA
t
OE
t
OD
V
V
IH
IL
OE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
SYMBOL
MIN
MAX
12
MIN
MAX
15
UNITS
ns
t
t
AA
25
30
OFF
0
0
t
t
ACH
12
38
0
15
45
0
ns
RAC
50
60
ns
t
t
AR
ns
RAD
9
9
12
10
60
104
14
0
ns
t
t
ASC
ns
RAH
ns
t
t
ASR
0
0
ns
RAS
50
84
11
0
10,000
10,000
ns
t
t
CAC
13
15
ns
RC
ns
t
t
CAH
8
8
10
10
0
ns
RCD
ns
t
t
CAS
10,000
10,000
ns
RCH
ns
t
t
CLZ
0
ns
RCS
0
0
ns
t
t
CRP
5
5
ns
RP
30
0
40
0
ns
t
t
CSH
38
0
45
0
ns
RRH
ns
t
t
OD
12
12
15
15
ns
RSH
13
15
ns
t
OE
ns
t
NOTE: 1. OFF is referenced from rising edge of RAS# or CAS#, whichever occurs last.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©1999,MicronTechnology,Inc.
15
MICRON [ MICRON TECHNOLOGY ]
