Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Figure 8: Single-Word Asynchronous Read Waveform
R1
R2
Address [A]
R8
R3
CEx [E]
R9
R4
OE# [G]
WE# [W]
R7
R10
R6
DQ[15:0] [Q]
R13
R11
R5
R12
BYTE# [F]
RP# [P]
Notes:
1.
CEX low is defined as the combination of pins CE0, CE1, and CE2 that enable the device. CEX high is defined as the
combination of pins CE0, CE1, and CE2 that disable the device (see Table 17, “Chip Enable Truth Table for 32-
, 64-, 128-Mb” on page 30).
2.
When reading the flash array a faster tGLQV (R16) applies. For non-array reads, R4 applies (i.e., Status Register reads,
query reads, or device identifier reads).
Figure 9: 8-Word Asynchronous Page Mode Read
R1
R2
A[MAX:4] [A]
000
R3
001
110
111
A[3:1] [A]
CEx [E]
OE# [G]
R4
R8
WE# [W]
R7
R10
R15
R10
R6
R9
1
2
7
8
DQ[15:0] [Q]
RP# [P]
R5
BYTE# [F]
Notes:
1.
CEX low is defined as the combination of pins CE0, CE1, and CE2 that enable the device. CEX high is defined as the
combination of pins CE0, CE1, and CE2 that disable the device (see Table 17, “Chip Enable Truth Table for 32-
, 64-, 128-Mb” on page 30).
2.
In this diagram, BYTE# is asserted high.
Jan 2011
208032-03
Datasheet
25
MICRON [ MICRON TECHNOLOGY ]
