Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
7.1
Read Specifications
Table 11: Read Operations
Asynchronous Specifications VCC = 2.7 V–3.6 V (3) and VCCQ = 2.7 V–3.6 V(3)
#
Sym
tAVAV
Parameter
Read/Write Cycle Time
Density
Min
Max
Unit
Notes
R1
75
—
—
—
—
—
—
0
—
75
ns
ns
ns
ns
1,2
1,2
R2
R3
R4
tAVQV
tELQV
tGLQV
Address to Output Delay
CEX to Output Delay
All
75
1,2
OE# to Non-Array Output Delay
25
1,2,4
1,2
32 Mbit
64 Mbit
128 Mbit
150
180
210
—
R5
tPHQV
RP# High to Output Delay
ns
1,2
1,2
R6
R7
R8
R9
tELQX
tGLQX
tEHQZ
tGHQZ
CEX to Output in Low Z
ns
ns
ns
ns
1,2,5
1,2,5
1,2,5
1,2,5
OE# to Output in Low Z
0
—
CEX High to Output in High Z
OE# High to Output in High Z
—
—
25
15
Output Hold from Address, CEX, or OE#
Change, Whichever Occurs First
R10
tOH
0
—
ns
1,2,5
All
R11
R12
R13
R14
R15
R16
t
ELFL/tELFH
CEX Low to BYTE# High or Low
—
—
—
0
10
1
ns
µs
µs
ns
ns
ns
1,2,5
1,2
tFLQV/tFHQV BYTE# to Output Delay
tFLQZ
tEHEL
tAPA
BYTE# to Output in High Z
CEx High to CEx Low
1
1,2,5
1,2,5
5, 6
—
25
25
Page Address Access Time
OE# to Array Output Delay
—
—
tGLQV
1,2,4
Notes:
1.
CE low is defined as the combination of pins CE0, CE1 and CE2 that enable the device. CE high is defined as the
X X
combination of pins CE0, CE1, and CE2 that disable the device (see Table 17, “Chip Enable Truth Table for 32-
, 64-, 128-Mb” on page 30).
2.
3.
See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
OE# may be delayed up to tELQV-tGLQV after the falling edge of CE (see note 1 and Table 17, “Chip Enable Truth
X
Table for 32-, 64-, 128-Mb” on page 30) without impact on tELQV
See Figure 13, “AC Input/Output Reference Waveform” on p.age 29 and Figure 14, “Transient
Equivalent Testing Load Circuit” on page 29 for testing characteristics.
Sampled, not 100% tested.
4.
5.
6.
For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV).
Datasheet
24
Jan 2011
208032-03
MICRON [ MICRON TECHNOLOGY ]
