Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Table 12: Write Operations
Valid for All
Speeds
#
Symbol
Parameter
Density
Unit
Notes
Min
Max
32 Mbit
64 Mbit
128 Mbit
150
180
210
0
—
—
—
—
—
—
—
—
—
—
—
—
—
500
W1
t
t
PHWL (tPHEL
)
RP# High Recovery to WE# (CEX) Going Low
1,2,3,4
W2
W3
ELWL (tWLEL
)
CEX (WE#) Low to WE# (CEX) Going Low
Write Pulse Width
1,2,3,5
1,2,3,5
1,2,3,6
1,2,3,6
1,2,3
tWP
60
50
55
0
W4
tDVWH (tDVEH
)
Data Setup to WE# (CEX) Going High
Address Setup to WE# (CEX) Going High
CEX (WE#) Hold from WE# (CEX) High
Data Hold from WE# (CEX) High
Address Hold from WE# (CEX) High
Write Pulse Width High
W5
tAVWH (tAVEH
)
W6
tWHEH (tEHWH
tWHDX (tEHDX
)
ns
W7
)
0
1,2,3
All
W8
t
WHAX (tEHAX
tWPH
VPWH (tVPEH
WHGL (tEHGL
)
0
1,2,3
W9
30
0
1,2,3,7
1,2,3,4
1,2,3,8
1,2,3,9
W11
W12
W13
t
)
)
VPEN Setup to WE# (CEX) Going High
Write Recovery before Read
t
35
—
tWHRL (tEHRL
)
WE# (CEX) High to STS Going Low
1,2,3,4,
9,10
W15
tQVVL
VPEN Hold from Valid SRD, STS Going High
0
—
Notes:
1.
CE low is defined as the combination of pins CE0, CE1, and CE2 that enable the device. CE high is defined as the
X X
combination of pins CE0, CE1, and CE2 that disable the device (see Table 17, “Chip Enable Truth Table for
32-, 64-, 128-Mb” on page 30).
2.
Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics–Read-Only Operations.
3.
4.
5.
A write operation can be initiated and terminated with either CEX or WE#.
Sampled, not 100% tested.
Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low last) to CEX or WE# going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH
.
6.
7.
Refer to Table 18, “Enhanced Configuration Register” on page 32 for valid AIN and DIN for block erase,
program, or lock-bit configuration.
Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE# going
low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL
.
8.
9.
10.
For array access, tAVQV is required in addition to tWHGL for any accesses after a write.
STS timings are based on STS configured in its RY/BY# default mode.
VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success (SR[5:3,1]
= 0).
Datasheet
26
Jan 2011
208032-03
MICRON [ MICRON TECHNOLOGY ]
