Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
7.0
AC Characteristics
Timing symbols used in the timing diagrams within this document conform to the
following convention.
Figure 7: Timing Signal Naming Convention
E L Q V
t
Source Signal
Source State
Target State
Target Signal
Table 10: Timing Signal Name Decoder
Signal
Code
State
Code
Address
A
Q
D
E
High
H
L
Data - Read
Data - Write
Low
High-Z
Low-Z
Valid
Z
X
V
I
Chip Enable (CE)
Output Enable (OE#)
Write Enable (WE#)
Status (STS)
G
W
R
P
Invalid
Reset (RP#)
Byte Enable (BYTE#)
Erase/Program/Block Lock
F
V
Enable (VPEN
)
Note:
Exceptions to this convention include tACC and tAPA. tACC is a generic timing symbol that
refers to the aggregate initial-access delay as determined by tAVQV, tELQV, and tGLQV
(whichever is satisfied last) of the flash device. tAPA is specified in the flash device’s
data sheet, and is the address-to-data delay for subsequent page-mode reads.
Jan 2011
208032-03
Datasheet
23
MICRON [ MICRON TECHNOLOGY ]
