Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Table 14: Reset Specifications
#
Symbol
Parameter
Min
Max
Unit
Notes
RP# is asserted during block erase,
program or lock-bit configuration
operation
RP# Pulse Low Time
(If RP# is tied to VCC, this
specification is not
applicable)
25
—
µs
1
P1
tPLPH
RP# is asserted during read
100
—
—
100
—
ns
ns
µs
1
RP# High to Reset during Block Erase, Program, or Lock-Bit
Configuration
P2
P3
tPHRH
1,2
—
tVCCPH
Vcc Power Valid to RP# de-assertion (high)
60
Notes:
1.
2.
These specifications are valid for all product versions (packages and speeds).
A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid.
7.4
AC Test Conditions
Figure 13: AC Input/Output Reference Waveform
VCCQ
Input VCCQ/2
0.0
Test Points
VCCQ/2 Output
Note: AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at
CCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.
V
Figure 14: Transient Equivalent Testing Load Circuit
Device
Under Test
Out
CL
Note: CL Includes Jig Capacitance
Table 15: Test Configuration
Test Configuration
CL (pF)
VCCQ = VCCQMIN
30
Jan 2011
208032-03
Datasheet
29
MICRON [ MICRON TECHNOLOGY ]
