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JS28F128P30TF75A 参数 Datasheet PDF下载

JS28F128P30TF75A图片预览
型号: JS28F128P30TF75A
PDF下载: 下载PDF文件 查看货源
内容描述: 恒忆Axcell P30-65nm闪存 [Numonyx Axcell P30-65nm Flash Memory]
分类和应用: 闪存
文件页数/大小: 90 页 / 1194 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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P30-65nm SBC  
bits, as long as the register remains unlocked. Additionally, because the Lock Register  
bits themselves are OTP, when programmed, Lock Register bits cannot be erased.  
Therefore, when a OTP Register is locked, it cannot be unlocked.  
Figure 14: OTP Register Map  
0x109  
128-bit OTP Register 16  
(User-Programmable)  
0x102  
0x91  
128-bit OTP Register 1  
(User-Programmable)  
0x8A  
0x89  
Lock Register 1  
15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
0x88  
64-bit Segment  
(User-Programmable)  
0x85  
0x84  
128-Bit OTP Register 0  
64-bit Segment  
(Factory-Programmed)  
0x81  
0x80  
Lock Register 0  
15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
11.3.1  
Reading the OTP Registers  
The OTP Registers can be read from OTP-RA address. To read the OTP Register, first  
issue the Read Device Identifier command at OTP-RA address to place the device in the  
Read Device Identifier state (see Section 6.2, “Device Command Bus Cycles” on  
page 20). Next, perform a read operation using the address offset corresponding to the  
register to be read. Table 8, “Device Identifier Information” on page 22 shows the  
address offsets of the OTP Registers and Lock Registers. OTP Registers and Lock  
Registers data is read 16 bits at a time.  
Datasheet  
41  
Apr 2010  
OrderNumber:208033-02  
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