P30-65nm SBC
Figure 11: Example Latency Count Setting Using Code 3
tData
0
1
2
3
4
CLK
CE#
ADV#
Address
A[MAX:0]
A[MAX:1]
Code 3
High-Z
Data
D[15:0]
R103
11.2.3
End of Word Line (EOWL) Considerations
The delay may occur when a burst sequence access crosses a 8-word boundary. That
is, A[3:1] of start address does not equal 0x0. Figure 12, “End of Wordline Timing
Diagram” on page 37 illustrates the end of wordline WAIT state(s), which occur after
the first 8-word boundary is reached. The number of data words and the number of
WAIT states is summarized in Table 15, “End of Wordline Data and WAIT state
Comparison” on page 38 for both P30-130nm and P30-65nm SBC devices.
Figure 12: End of Wordline Timing Diagram
Latency Count
CLK
A[Max:1]
DQ[15:0]
Data
Data
Data
ADV#
OE#
WAIT
EOWL
Datasheet
37
Apr 2010
OrderNumber:208033-02
MICRON [ MICRON TECHNOLOGY ]
