P30-65nm SBC
Table 17: Burst Sequence Word Ordering (Sheet 2 of 2)
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1-2-3-4
2-3-4-5
3-4-5-6
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9
1-2-3-4-5…15-16
2-3-4-5-6…16-17
3-4-5-6-7…17-18
4-5-6-7-8…18-19
5-6-7-8-9…19-20
6-7-8-9-10…20-21
7-8-9-10-11…21-22
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
3-4-5-6-7-8-9-10
4-5-6-7-8-9-10-11
5-6-7-8-9-10-11-12
6-7-8-9-10-11-12-13
7-8-9-10-11-12-13-14
4-5-6-7-8-9-10…
5-6-7-8-9-10-11…
6-7-8-9-10-11-12-…
7-8-9-10-11-12-13…
14-15-16-17-18-19-20-
…
14
15
1
1
14-15-16-17-18…28-29
15-16-17-18-19…29-30
15-16-17-18-19-20-21-
…
11.2.8
11.2.9
Clock Edge (RCR.6)
The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK.
This clock edge is used at the start of a burst cycle, to output synchronous data, and to
assert/deassert WAIT.
Burst Wrap (RCR.3)
The Burst Wrap (BW) bit determines whether 4, 8, or 16-word burst length accesses
wrap within the selected word-length boundaries or cross word-length boundaries.
When BW is set, burst wrapping does not occur (default). When BW is cleared, burst
wrapping occurs.
11.2.10
Burst Length (RCR[2:0])
The Burst Length bits (BL[2:0]) select the linear burst length for all synchronous burst
reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word or
continuous word.
Continuous burst accesses are linear only, and do not wrap within any word length
boundaries (see Table 17, “Burst Sequence Word Ordering” on page 39). When a burst
cycle begins, the device outputs synchronous burst data until it reaches the end of the
“burstable” address space.
11.3
One-Time Programmable (OTP) Registers
The device contains 17 OTP Registers that can be used to implement system security
measures and/or device identification. Each OTP Register can be individually locked.
The first 128-bit OTP Register is comprised of two 64-bit (8-word) segments. The lower
64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit
number. The upper 64-bit segment, as well as the other sixteen 128-bit OTP Registers,
are blank. Users can program these registers as needed. Once programmed, users can
then lock the OTP Register(s) to prevent additional bit programming (see Figure 14,
“OTP Register Map” on page 41).
Each OTP Register has an associated Lock Register bit. When a Lock Register bit is
programmed, the associated OTP Register can only be read; it can no longer be
programmed. Each OTP Register can be accessed multiple times to program individual
Datasheet
40
Apr 2010
Order Number: 208033-02
MICRON [ MICRON TECHNOLOGY ]
