P30-65nm SBC
Table 15: End of Wordline Data and WAIT state Comparison
P30-130nm
P30-65nm SBC
Latency Count
Data States
WAIT States
Data States
WAIT States
1
2
3
4
5
6
7
Not Supported
Not Supported
0 to 1
Not Supported
Not Supported
Not Supported
Not Supported
0 to 2
4
4
4
4
4
4
0 to 2
0 to 3
0 to 4
0 to 5
8
8
8
8
8
0 to 3
0 to 4
0 to 5
0 to 6
0 to 6
11.2.4
WAIT Polarity (RCR.10)
The WAIT Polarity bit (WP), RCR.10 determines the asserted level (VOH or VOL) of WAIT.
When WP is set, WAIT is asserted high. When WP is cleared, WAIT is asserted low
(default). WAIT changes state on valid clock edges during active bus cycles (CE#
asserted, OE# asserted, RST# deasserted).
Table 16: WAIT Functionality Table
Condition
WAIT
Notes
CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’
CE# =’0’, OE# = ‘0’
High-Z
Active
1
1
Synchronous Array Reads
Synchronous Non-Array Reads
All Asynchronous Reads
All Writes
Active
1
Active
1
Deasserted
High-Z
1
1,2
Notes:
1.
2.
Active: WAIT is asserted until data becomes valid, then deasserts.
When OE# = V during writes, WAIT = High-Z.
IH
11.2.5
Data Output Configuration (RCR.9)
The Data Output Configuration (DOC) bit, RCR.9 determines whether a data word
remains valid on the data bus for one or two clock cycles. This period of time is called
the “data cycle”. When DOC is set, output data is held for two clocks (default). When
DOC is cleared, output data is held for one clock (see Figure 13, “Data Hold Timing” on
page 39). The processor’s data setup time and the flash memory’s clock-to-data output
delay should be considered when determining whether to hold output data for one or
two clocks. A method for determining the Data Hold configuration is shown below:
To set the device at one clock data hold for subsequent reads, the following condition
must be satisfied:
t
CHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)
tDATA = Data set up to Clock (defined by CPU)
For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming
tCHQV = 20 ns and tDATA = 4 ns. Applying these values to the formula above:
20 ns + 4 ns ≤ 25 ns
The equation is satisfied and data will be available at every clock period with data hold
setting at one clock. If tCHQV (ns) + tDATA (ns) >One CLK Period (ns), data hold setting of
2 clock periods must be used.
Datasheet
38
Apr 2010
Order Number: 208033-02
MICRON [ MICRON TECHNOLOGY ]
