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JS28F128P30TF75A 参数 Datasheet PDF下载

JS28F128P30TF75A图片预览
型号: JS28F128P30TF75A
PDF下载: 下载PDF文件 查看货源
内容描述: 恒忆Axcell P30-65nm闪存 [Numonyx Axcell P30-65nm Flash Memory]
分类和应用: 闪存
文件页数/大小: 90 页 / 1194 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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P30-65nm SBC  
11.3.2  
Programming the OTP Registers  
To program an OTP Register, first issue the OTP Register Program Setup command at  
the device base address plus the offset address of the desired OTP Register location  
(OTP-RA: see Figure 14, “OTP Register Map” on page 41). Next, write the desired OTP  
Register data to the same OTP Register address. See Section 6.2, “Device Command  
Bus Cycles” on page 20.  
The device programs the 64-bit and Sixteen 128-bit user-programmable OTP Register  
data 16 bits at a time (see Figure 40, “OTP Register Programming Flowchart” on  
page 81). Issuing the OTP Register Program Setup command outside of the OTP  
Register’s address space causes a program error (SR.4 set). Attempting to program a  
locked OTP Register causes a program error (SR.4 set) and a lock error (SR.1 set).  
11.3.3  
Locking the OTP Registers  
Each OTP Register can be locked by programming its respective lock bit in the Lock  
Register. To lock an OTP Register, program the corresponding bit in the Lock Register by  
issuing the Lock Register Program Setup command, followed by the desired Lock  
Register data (see Section 6.2, “Device Command Bus Cycles” on page 20). The  
physical addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1.  
These addresses are used when programming the lock registers (see Table 8, “Device  
Identifier Information” on page 22).  
Bit 0 of Lock Register 0 is already programmed during the manufacturing process at  
Numonyx factory, locking the lower half segment of the first 128-bit OTP Register. Bit 1  
of Lock Register 0 can be programmed by user to the upper half segment of the first  
128-bit OTP Register. When programming Bit 1 of Lock Register 0, all other bits need to  
be left as ‘1’ such that the data programmed is 0xFFFD.  
Lock Register 1 controls the locking of the upper sixteen 128-bit OTP Registers. Each  
bit of Lock Register 1 corresponds to a specific 128-bit OTP Register; e.g.,  
programming LR1.0 locks the corresponding OTP Register 1.  
Caution:  
After being locked, the OTP Registers cannot be unlocked.  
Datasheet  
42  
Apr 2010  
Order Number: 208033-02  
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