P30-65nm SBC
12.0
Power and Reset Specifications
12.1
Power-Up and Power-Down
Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise
VCC and VCCQ should attain their minimum operating voltage before applying VPP.
Power supply transitions should only occur when RST# is low. This protects the device
from accidental programming or erasure during power transitions.
12.2
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
Table 18: Power and Reset
Num
Symbol
Parameter
RST# pulse width low
Min
Max
Unit
Notes
P1
t
100
-
-
ns
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
PLPH
RST# low to device reset during erase
RST# low to device reset during program
VCC Power valid to RST# de-assertion (high)
25
25
-
P2
t
t
PLRH
VCCPH
-
µs
P3
60
Notes:
1.
2.
3.
4.
5.
6.
7.
These specifications are valid for all device versions (packages and speeds).
The device may reset if t is < t Min, but this is not guaranteed.
PLPH
PLPH
Not applicable if RST# is tied to VCC.
Sampled, but not 100% tested.
When RST# is tied to the VCC supply, device will not be ready until t
after VCC ≥ V
VCCPH
.
VCCPH
CCMIN
When RST# is tied to the VCCQ supply, device will not be ready until t
Reset completes within t
after VCC ≥ V
.
CCMIN
if RST# is asserted while no erase or program operation is executing.
PLPH
Datasheet
43
Apr 2010
OrderNumber:208033-02
MICRON [ MICRON TECHNOLOGY ]
