P30-65nm SBC
11.2.2
Latency Count (RCR[13:11])
The Latency Count (LC) bits tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the
first valid data word is driven onto DQ[15:0]. The input clock frequency is used to
determine this value and Figure 10 shows the data output latency for the different
settings of LC. The maximum Latency Count for P30-65nm SBC device would be Code 4
based on the Max clock frequency specification of 52MHz, and there will be zero WAIT
States when bursting within the word line. Please also refer to Section 11.2.3, “End of
Word Line (EOWL) Considerations” on page 37 for more information on EOWL.
Refer to Table 14, “LC and Frequency Support” on page 36 for Latency Code Settings.
Figure 10: First-Access Latency Count
CLK [C]
Valid
Address
Address [A]
ADV#[V]
Code 0 (Reserved)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
Code 1
(Reserved
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 2
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 3
Code 4
Code 5
Code 6
Code 7
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Table 14: LC and Frequency Support
Latency Count Settings
Frequency Support (MHz)
3
4
≤ 40
≤ 52
Datasheet
36
Apr 2010
Order Number: 208033-02
MICRON [ MICRON TECHNOLOGY ]
