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PIC24FJ32GA104T-I/PT 参数 Datasheet PDF下载

PIC24FJ32GA104T-I/PT图片预览
型号: PIC24FJ32GA104T-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 44分之28引脚, 16位通用闪存微控制器采用nanoWatt XLP技术 [28/44-Pin, 16-Bit General Purpose Flash Microcontrollers with nanoWatt XLP Technology]
分类和应用: 闪存微控制器
文件页数/大小: 308 页 / 2416 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC24FJ64GA104 FAMILY  
24-bit program word are used to contain the data. The  
upper 8 bits of any program space locations used as  
data should be programmed with ‘1111 1111’ or  
0000 0000’ to force a NOP. This prevents possible  
issues should the area of code ever be accidentally  
executed.  
4.3.3  
READING DATA FROM PROGRAM  
MEMORY USING PROGRAM SPACE  
VISIBILITY  
The upper 32 Kbytes of data space may optionally be  
mapped into any 16K word page of the program space.  
This provides transparent access of stored constant  
data from the data space without the need to use  
special instructions (i.e., TBLRDL/H).  
Note:  
PSV access is temporarily disabled during  
table reads/writes.  
Program space access through the data space occurs if  
the Most Significant bit (MSb) of the data space EA is ‘1’  
and program space visibility is enabled by setting the  
PSV bit in the CPU Control register (CORCON<2>). The  
location of the program memory space to be mapped  
into the data space is determined by the Program Space  
Visibility Page Address register (PSVPAG). This 8-bit  
register defines any one of 256 possible pages of  
16K words in program space. In effect, PSVPAG func-  
tions as the upper 8 bits of the program memory  
address, with the 15 bits of the EA functioning as the  
lower bits. Note that by incrementing the PC by 2 for  
each program memory word, the lower 15 bits of data  
space addresses directly map to the lower 15 bits in the  
corresponding program space addresses.  
For operations that use PSV and are executed outside  
a REPEATloop, the MOV and MOV.Dinstructions will  
require one instruction cycle in addition to the specified  
execution time. All other instructions will require two  
instruction cycles in addition to the specified execution  
time.  
For operations that use PSV which are executed inside  
a REPEAT loop, there will be some instances that  
require two instruction cycles in addition to the  
specified execution time of the instruction:  
• Execution in the first iteration  
• Execution in the last iteration  
• Execution prior to exiting the loop due to an  
interrupt  
• Execution upon re-entering the loop after an  
interrupt is serviced  
Data reads to this area add an additional cycle to the  
instruction being executed, since two program memory  
fetches are required.  
Any other iteration of the REPEAT loop will allow the  
instruction accessing data, using PSV, to execute in a  
single cycle.  
Although each data space address, 8000h and higher,  
maps directly into a corresponding program memory  
address (see Figure 4-7), only the lower 16 bits of the  
FIGURE 4-7:  
PROGRAM SPACE VISIBILITY OPERATION  
When CORCON<2> = 1and EA<15> = 1:  
Program Space  
Data Space  
PSVPAG  
02  
23  
15  
0
000000h  
0000h  
Data EA<14:0>  
010000h  
018000h  
The data in the page  
designated by  
PSVPAG is mapped  
into the upper half of  
the data memory  
space....  
8000h  
PSV Area  
...while the lower  
15 bits of the EA  
specify an exact  
address within the  
PSV area. This  
FFFFh  
corresponds exactly to  
the same lower 15 bits  
of the actual program  
space address.  
800000h  
DS39951C-page 50  
2010 Microchip Technology Inc.  
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