PIC24FJ64GA104 FAMILY
In Synchronous mode, the module begins performing
its compare or PWM operation as soon as its selected
clock source is enabled. Whenever an event occurs on
14.0 OUTPUT COMPARE WITH
DEDICATED TIMERS
the selected sync source, the module’s internal counter
is reset. In Trigger mode, the module waits for a sync
event from another internal module to occur before
allowing the counter to run.
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 35. “Output Capture with
Dedicated Timer” (DS39723).
Free-Running mode is selected by default or any time
that the SYNCSEL bits (OCxCON2<4:0>) are set to
‘00000’. Synchronous or Trigger modes are selected
any time the SYNCSEL bits are set to any value except
‘00000’. The OCTRIG bit (OCxCON2<7>) selects
either Synchronous or Trigger mode; setting the bit
selects Trigger mode operation. In both modes, the
SYNCSEL bits determine the sync/trigger source.
All devices in the PIC24FJ64GA104 family features
5 independent output compare modules. Each of these
modules offers a wide range of configuration and oper-
ating options for generating pulse trains on internal
device events, and can produce Pulse-Width Modulated
(PWM) waveforms for driving power applications.
14.1.2
CASCADED (32-BIT) MODE
Key features of the output compare module include:
By default, each module operates independently with
its own set of 16-bit Timer and Duty Cycle registers. To
increase the range, adjacent even and odd modules
can be configured to function as a single 32-bit module.
(For example, Modules 1 and 2 are paired, as are
Modules 3 and 4, and so on.) The odd-numbered
module (OCx) provides the Least Significant 16 bits of
the 32-bit register pairs and the even-numbered
module (OCy) provides the Most Significant 16 bits.
Wrap-arounds of the OCx registers cause an increment
of their corresponding OCy registers.
• Hardware-configurable for 32-bit operation in all
modes by cascading two adjacent modules
• Synchronous and Trigger modes of output
compare operation, with up to 21 user-selectable
trigger/sync sources available
• Two separate Period registers (a main register,
OCxR, and a secondary register, OCxRS) for
greater flexibility in generating pulses of varying
widths
• Configurable for single pulse or continuous pulse
generation on an output event or continuous
PWM waveform generation
Cascaded operation is configured in hardware by setting
the OC32 bit (OCxCON2<8>) for both modules.
• Up to 6 clock sources available for each module,
driving a separate internal 16-bit counter
14.1 General Operating Modes
14.1.1
SYNCHRONOUS AND TRIGGER
MODES
By default, the output compare module operates in a
Free-Running mode. The internal 16-bit counter,
OCxTMR, runs counts up continuously, wrapping
around from FFFFh to 0000h on each overflow with its
period synchronized to the selected external clock
source. Compare or PWM events are generated each
time a match between the internal counter and one of
the Period registers occurs.
2010 Microchip Technology Inc.
DS39951C-page 155
MICROCHIP [ MICROCHIP ]
