PIC18F2480/2580/4480/4580
TABLE 6-2:
REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
Value on Detailson
POR, BOR Page:
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXB1D1
TXB1D17
TXB1D07
—
TXB1D16
TXB1D06
TXRTR
EID6
TXB1D15
TXB1D05
—
TXB1D14
TXB1D04
—
TXB1D13
TXB1D03
DLC3
TXB1D12
TXB1D02
DLC2
EID2
TXB1D11
TXB1D01
DLC1
TXB1D10
TXB1D00
DLC0
xxxx xxxx 60, 290
xxxx xxxx 60, 290
-x-- xxxx 60, 291
xxxx xxxx 60, 290
xxxx xxxx 60, 289
xxx- x-xx 60, 289
xxxx xxxx 60, 289
0000 0-00 60, 288
xxxx xxxx 60, 290
xxxx xxxx 61, 290
xxxx xxxx 61, 290
xxxx xxxx 61, 290
xxxx xxxx 61, 290
xxxx xxxx 61, 290
xxxx xxxx 61, 290
xxxx xxxx 61, 290
-x-- xxxx 61, 291
xxxx xxxx 61, 290
xxxx xxxx 61, 289
xxxx x-xx 61, 289
xxx- x-xx 61, 289
0000 0-00 61, 288
xxxx xxxx 61, 310
xxxx xxxx 61, 310
xxx- x-xx 61, 310
xxxx xxxx 61, 310
xxxx xxxx 61, 310
xxxx xxxx 61, 310
xxx- x-xx 61, 310
xxxx xxxx 61, 309
xxxx xxxx 61, 309
xxxx xxxx 61, 309
xxx- x-xx 61, 308
xxxx xxxx 61, 308
xxxx xxxx 61, 309
xxxx xxxx 61, 309
xxx- x-xx 61, 308
xxxx xxxx 61, 308
xxxx xxxx 61, 309
xxxx xxxx 61, 309
xxx- x-xx 62, 308
TXB1D0
TXB1DLC
TXB1EIDL
TXB1EIDH
TXB1SIDL
TXB1SIDH
TXB1CON
TXB2D7
EID7
EID5
EID4
EID3
EID1
EID0
EID15
SID2
EID14
SID1
EID13
SID0
EID12
—
EID11
EID10
—
EID9
EID8
EXIDE
SID6
EID17
SID4
EID16
SID3
SID10
TXBIF
TXB2D77
TXB2D67
TXB2D57
TXB2D47
TXB2D37
TXB2D27
TXB2D17
TXB2D07
—
SID9
SID8
SID7
SID5
TXABT
TXB2D76
TXB2D66
TXB2D56
TXB2D46
TXB2D36
TXB2D26
TXB2D16
TXB2D06
TXRTR
EID6
TXLARB
TXB2D75
TXB2D65
TXB2D55
TXB2D45
TXB2D35
TXB2D25
TXB2D15
TXB2D05
—
TXERR
TXB2D74
TXB2D64
TXB2D54
TXB2D44
TXB2D34
TXB2D24
TXB2D14
TXB2D04
—
TXREQ
TXB2D73
TXB2D63
TXB2D53
TXB2D43
TXB2D33
TXB2D23
TXB2D13
TXB2D03
DLC3
—
TXPRI1
TXB2D71
TXB2D61
TXB2D51
TXB2D41
TXB2D31
TXB2D21
TXB2D11
TXB2D01
DLC1
TXPRI0
TXB2D70
TXB2D60
TXB2D50
TXB2D40
TXB2D30
TXB2D20
TXB2D10
TXB2D00
DLC0
TXB2D72
TXB2D62
TXB2D52
TXB2D42
TXB2D32
TXB2D22
TXB2D12
TXB2D02
DLC2
EID2
TXB2D6
TXB2D5
TXB2D4
TXB2D3
TXB2D2
TXB2D1
TXB2D0
TXB2DLC
TXB2EIDL
TXB2EIDH
TXB2SIDL
TXB2SIDH
TXB2CON
RXM1EIDL
RXM1EIDH
RXM1SIDL
RXM1SIDH
RXM0EIDL
RXM0EIDH
RXM0SIDL
RXM0SIDH
RXF5EIDL
RXF5EIDH
RXF5SIDL
RXF5SIDH
RXF4EIDL
RXF4EIDH
RXF4SIDL
RXF4SIDH
RXF3EIDL
RXF3EIDH
RXF3SIDL
EID7
EID5
EID4
EID3
EID1
EID0
EID15
SID2
EID14
SID1
EID13
SID0
EID12
—
EID11
EID10
—
EID9
EID8
EXIDE
SID6
EID17
SID4
EID16
SID3
SID10
TXBIF
EID7
SID9
SID8
SID7
SID5
TXABT
EID6
TXLARB
EID5
TXERR
EID4
TXREQ
EID3
—
TXPRI1
EID1
TXPRI0
EID0
EID2
EID15
SID2
EID14
SID1
EID13
SID0
EID12
—
EID11
EID10
—
EID9
EID8
EXIDEN
SID6
EID17
SID4
EID16
SID3
SID10
EID7
SID9
SID8
SID7
SID5
EID6
EID5
EID4
EID3
EID2
EID1
EID0
EID15
SID2
EID14
SID1
EID13
SID0
EID12
—
EID11
EID10
—
EID9
EID8
EXIDEN
SID6
EID17
SID4
EID16
SID3
SID10
EID7
SID9
SID8
SID7
SID5
EID6
EID5
EID4
EID3
EID2
EID1
EID0
EID15
SID2
EID14
SID1
EID13
SID0
EID12
—
EID11
EID10
—
EID9
EID8
EXIDEN
SID6
EID17
SID4
EID16
SID3
SID10
EID7
SID9
SID8
SID7
SID5
EID6
EID5
EID4
EID3
EID2
EID1
EID0
EID15
SID2
EID14
SID1
EID13
SID0
EID12
—
EID11
EID10
—
EID9
EID8
EXIDEN
SID6
EID17
SID4
EID16
SID3
SID10
EID7
SID9
SID8
SID7
SID5
EID6
EID5
EID4
EID3
EID2
EID1
EID0
EID15
SID2
EID14
SID1
EID13
SID0
EID12
—
EID11
EID10
—
EID9
EID8
EXIDEN
EID17
EID16
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices;
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.
DS39637D-page 88
© 2009 Microchip Technology Inc.
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