PIC18F2480/2580/4480/4580
TABLE 6-2:
REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
Value on Detailson
POR, BOR Page:
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
B4D2(8)
B4D1(8)
B4D0(8)
B4D27
B4D17
B4D07
—
B4D26
B4D16
B4D06
RXRTR
B4D25
B4D15
B4D05
RB1
B4D24
B4D14
B4D04
RB0
B4D23
B4D13
B4D03
DLC3
B4D22
B4D12
B4D02
DLC2
B4D21
B4D11
B4D01
DLC1
B4D20
B4D10
B4D00
DLC0
xxxx xxxx 63, 305
xxxx xxxx 63, 305
xxxx xxxx 62, 305
-xxx xxxx 63, 307
B4DLC(8)
Receive mode
B4DLC(8)
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
-x-- xxxx 63, 307
Transmit mode
B4EIDL(8)
B4EIDH(8)
B4SIDL(8)
EID7
EID15
SID2
EID6
EID14
SID1
EID5
EID13
SID0
EID4
EID12
SRR
EID3
EID11
EXID
EID2
EID10
—
EID1
EID9
EID0
EID8
xxxx xxxx 63, 305
xxxx xxxx 63, 304
xxxx x-xx 63, 303
EID17
EID16
Receive mode
B4SIDL(8)
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
xxx- x-xx 63, 303
Transmit mode
B4SIDH(8)
B4CON(8)
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx 63, 302
0000 0000 63, 301
RXFUL
RXM1
RXRTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
Receive mode
B4CON(8)
TXBIF
TXABT
TXLARB
TXERR
TXREQ
RTREN
TXPRI1
TXPRI0
0000 0000 63, 301
Transmit mode
B3D7(8)
B3D6(8)
B3D5(8)
B3D4(8)
B3D3(8)
B3D2(8)
B3D1(8)
B3D0(8)
B3D77
B3D67
B3D57
B3D47
B3D37
B3D27
B3D17
B3D07
—
B3D76
B3D66
B3D56
B3D46
B3D36
B3D26
B3D16
B3D06
RXRTR
B3D75
B3D65
B3D55
B3D45
B3D35
B3D25
B3D15
B3D05
RB1
B3D74
B3D64
B3D54
B3D44
B3D34
B3D24
B3D14
B3D04
RB0
B3D73
B3D63
B3D53
B3D43
B3D33
B3D23
B3D13
B3D03
DLC3
B3D72
B3D62
B3D52
B3D42
B3D32
B3D22
B3D12
B3D02
DLC2
B3D71
B3D61
B3D51
B3D41
B3D31
B3D21
B3D11
B3D01
DLC1
B3D70
B3D60
B3D50
B3D40
B3D30
B3D20
B3D10
B3D00
DLC0
xxxx xxxx 63, 305
xxxx xxxx 63, 305
xxxx xxxx 63, 305
xxxx xxxx 63, 305
xxxx xxxx 63, 305
xxxx xxxx 63, 305
xxxx xxxx 63, 305
xxxx xxxx 63, 305
-xxx xxxx 63, 307
B3DLC(8)
Receive mode
B3DLC(8)
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
-x-- xxxx 63, 307
Transmit mode
B3EIDL(8)
B3EIDH(8)
B3SIDL(8)
EID7
EID15
SID2
EID6
EID14
SID1
EID5
EID13
SID0
EID4
EID12
SRR
EID3
EID11
EXID
EID2
EID10
—
EID1
EID9
EID0
EID8
xxxx xxxx 63, 305
xxxx xxxx 63, 304
xxxx x-xx 63, 303
EID17
EID16
Receive mode
B3SIDL(8)
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
xxx- x-xx 63, 303
Transmit mode
B3SIDH(8)
B3CON(8)
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx 63, 302
0000 0000 63, 301
RXFUL
RXM1
RXRTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
Receive mode
B3CON(8)
TXBIF
TXABT
TXLARB
TXERR
TXREQ
RTREN
TXPRI1
TXPRI0
0000 0000 63, 301
Transmit mode
B2D7(8)
B2D6(8)
B2D5(8)
B2D77
B2D67
B2D57
B2D76
B2D66
B2D56
B2D75
B2D65
B2D55
B2D74
B2D64
B2D54
B2D73
B2D63
B2D53
B2D72
B2D62
B2D52
B2D71
B2D61
B2D51
B2D70
B2D60
B2D50
xxxx xxxx 63, 305
xxxx xxxx 63, 305
xxxx xxxx 63, 305
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices;
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.
DS39637D-page 90
© 2009 Microchip Technology Inc.
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