PIC18F2480/2580/4480/4580
TABLE 6-2:
REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
Value on Detailson
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
Page:
B2D4(8)
B2D3(8)
B2D2(8)
B2D1(8)
B2D0(8)
B2D47
B2D37
B2D27
B2D17
B2D07
—
B2D46
B2D36
B2D26
B2D16
B2D06
RXRTR
B2D45
B2D35
B2D25
B2D15
B2D05
RB1
B2D44
B2D34
B2D24
B2D14
B2D04
RB0
B2D43
B2D33
B2D23
B2D13
B2D03
DLC3
B2D42
B2D32
B2D22
B2D12
B2D02
DLC2
B2D41
B2D31
B2D21
B2D11
B2D01
DLC1
B2D40
B2D30
B2D20
B2D10
B2D00
DLC0
xxxx xxxx 63, 305
xxxx xxxx 63, 305
xxxx xxxx 63, 305
xxxx xxxx 64, 305
xxxx xxxx 64, 305
-xxx xxxx 64, 307
B2DLC(8)
Receive mode
B2DLC(8)
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
-x-- xxxx 64, 307
Transmit mode
B2EIDL(8)
B2EIDH(8)
B2SIDL(8)
EID7
EID15
SID2
EID6
EID14
SID1
EID5
EID13
SID0
EID4
EID12
SRR
EID3
EID11
EXID
EID2
EID10
—
EID1
EID9
EID0
EID8
xxxx xxxx 64, 305
xxxx xxxx 64, 304
xxxx x-xx 64, 303
EID17
EID16
Receive mode
B2SIDL(8)
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
xxx- x-xx 64, 303
Transmit mode
B2SIDH(8)
B2CON(8)
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx 64, 302
0000 0000 64, 301
RXFUL
RXM1
RXRTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
Receive mode
B2CON(8)
TXBIF
RXM1
TXLARB
TXERR
TXREQ
RTREN
TXPRI1
TXPRI0
0000 0000 64, 301
Transmit mode
B1D7(8)
B1D6(8)
B1D5(8)
B1D4(8)
B1D3(8)
B1D2(8)
B1D1(8)
B1D0(8)
B1D77
B1D67
B1D57
B1D47
B1D37
B1D27
B1D17
B1D07
—
B1D76
B1D66
B1D56
B1D46
B1D36
B1D26
B1D16
B1D06
RXRTR
B1D75
B1D65
B1D55
B1D45
B1D35
B1D25
B1D15
B1D05
RB1
B1D74
B1D64
B1D54
B1D44
B1D34
B1D24
B1D14
B1D04
RB0
B1D73
B1D63
B1D53
B1D43
B1D33
B1D23
B1D13
B1D03
DLC3
B1D72
B1D62
B1D52
B1D42
B1D32
B1D22
B1D12
B1D02
DLC2
B1D71
B1D61
B1D51
B1D41
B1D31
B1D21
B1D11
B1D01
DLC1
B1D70
B1D60
B1D50
B1D40
B1D30
B1D20
B1D10
B1D00
DLC0
xxxx xxxx 64, 305
xxxx xxxx 64, 305
xxxx xxxx 64, 305
xxxx xxxx 64, 305
xxxx xxxx 64, 305
xxxx xxxx 64, 305
xxxx xxxx 64, 305
xxxx xxxx 64, 305
-xxx xxxx 64, 307
B1DLC(8)
Receive mode
B1DLC(8)
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
-x-- xxxx 64, 307
Transmit mode
B1EIDL(8)
B1EIDH(8)
B1SIDL(8)
EID7
EID15
SID2
EID6
EID14
SID1
EID5
EID13
SID0
EID4
EID12
SRR
EID3
EID11
EXID
EID2
EID10
—
EID1
EID9
EID0
EID8
xxxx xxxx 64, 305
xxxx xxxx 64, 304
xxxx x-xx 64, 303
EID17
EID16
Receive mode
B1SIDL(8)
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
xxx- x-xx 64, 303
Transmit mode
B1SIDH(8)
B1CON(8)
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx 64, 302
0000 0000 64, 301
RXFUL
RXM1
RXRTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
Receive mode
B1CON(8)
TXBIF
TXABT
TXLARB
TXERR
TXREQ
RTREN
TXPRI1
TXPRI0
0000 0000 64, 301
Transmit mode
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices;
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.
© 2009 Microchip Technology Inc.
DS39637D-page 91
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