PIC18F2480/2580/4480/4580
TABLE 6-2:
REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
Value on Detailson
POR, BOR Page:
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTE(3)
PORTD(3)
PORTC
—
—
—
—
RE3(5)
RE2(3)
RE1(3)
RE0(3)
---- xxxx 58, 150
xxxx xxxx 58, 143
xxxx xxxx 58, 141
xxxx xxxx 58, 138
xx00 0000 58, 135
PORTD Data Direction Register
PORTC Data Direction Register
PORTB Data Direction Register
RA7(6)
MDSEL1
TEC7
PORTB
PORTA
RA6(6)
MDSEL0
TEC6
PORTA Data Direction Register
ECANCON
TXERRCNT
RXERRCNT
FIFOWM
TEC5
EWIN4
TEC4
REC4
TXBP
EWIN3
TEC3
REC3
RXBP
EWIN2
TEC2
EWIN1
TEC1
EWIN0
TEC0
0001 000
58, 286
0000 0000 58, 291
0000 0000 58, 299
0000 0000 58, 287
REC7
REC6
REC5
REC2
REC1
REC0
COMSTAT
Mode 0
RXB0OVFL RXB1OVFL
TXBO
TXWARN
RXWARN
EWARN
COMSTAT
Mode 1
—
RXBnOVFL
TXBO
TXBO
TXBP
TXBP
RXBP
RXBP
TXWARN
TXWARN
RXWARN
RXWARN
EWARN
-000 0000 58, 287
COMSTAT
Mode 2
FIFOEMPTY RXBnOVFL
EWARN
—
0000 0000 58, 287
--00 ---- 58, 320
CIOCON
—
—
ENDRHI
—
CANCAP
—
—
—
—
—
BRGCON3
BRGCON2
BRGCON1
WAKDIS
SEG2PHTS
SJW1
WAKFIL
SAM
SEG2PH2
PRSEG2
BRP2
SEG2PH1
PRSEG1
BRP1
SEG2PH0 00-- -000 59, 319
SEG1PH2 SEG1PH1
SEG1PH0
BRP3
WIN2(7)
PRSEG0
0000 0000 59, 318
0000 0000 59, 317
1000 000- 59, 282
SJW0
BRP5
BRP4
ABAT
BRP0
(7)
CANCON
Mode 0
REQOP2
REQOP1
REQOP0
WIN1(7)
WIN0(7)
—
(7)
(7)
(7)
(7)
CANCON
Mode 1
REQOP2
REQOP2
REQOP1
REQOP1
REQOP0
REQOP0
ABAT
ABAT
—
—
—
—
1000 ---- 59, 282
1000 0000 59, 282
000- 0000 59, 283
CANCON
Mode 2
FP3(7)
FP2(7)
FP1(7)
FP0(7)
(7)
(7)
CANSTAT
Mode 0
OPMODE2 OPMODE1 OPMODE0
—
ICODE3(7)
ICODE2(7)
EICODE2(7)
ICODE1(7)
—
CANSTAT
Modes 1, 2
OPMODE2 OPMODE1 OPMODE0 EICODE4(7) EICODE3(7)
EICODE1(7) EICODE0(7) 0000 0000 59, 283
RXB0D7
RXB0D6
RXB0D5
RXB0D4
RXB0D3
RXB0D2
RXB0D1
RXB0D0
RXB0DLC
RXB0EIDL
RXB0EIDH
RXB0SIDL
RXB0SIDH
RXB0D77
RXB0D67
RXB0D57
RXB0D47
RXB0D37
RXB0D27
RXB0D17
RXB0D07
—
RXB0D76
RXB0D66
RXB0D56
RXB0D46
RXB0D36
RXB0D26
RXB0D16
RXB0D06
RXRTR
EID6
RXB0D75
RXB0D65
RXB0D55
RXB0D45
RXB0D35
RXB0D25
RXB0D15
RXB0D05
RB1
RXB0D74
RXB0D64
RXB0D54
RXB0D44
RXB0D34
RXB0D24
RXB0D14
RXB0D04
RB0
RXB0D73
RXB0D63
RXB0D53
RXB0D43
RXB0D33
RXB0D23
RXB0D13
RXB0D03
DLC3
RXB0D72
RXB0D62
RXB0D52
RXB0D42
RXB0D32
RXB0D22
RXB0D12
RXB0D02
DLC2
RXB0D71
RXB0D61
RXB0D51
RXB0D41
RXB0D31
RXB0D21
RXB0D11
RXB0D01
DLC1
RXB0D70 xxxx xxxx 59, 298
RXB0D60 xxxx xxxx 59, 298
RXB0D50 xxxx xxxx 59, 298
RXB0D40 xxxx xxxx 59, 298
RXB0D30 xxxx xxxx 59, 298
RXB0D20 xxxx xxxx 59, 298
RXB0D10 xxxx xxxx 59, 298
RXB0D00 xxxx xxxx 59, 298
DLC0
EID0
EID8
EID16
SID3
-xxx xxxx 59, 298
xxxx xxxx 59, 297
xxxx xxxx 59, 297
xxxx x-xx 59, 297
xxxx xxxx 59, 296
EID7
EID5
EID4
EID3
EID2
EID1
EID15
EID14
EID13
EID12
EID11
EID10
EID9
SID2
SID1
SID0
SRR
EXID
—
EID17
SID10
SID9
SID8
SID7
SID6
SID5
SID4
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices;
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.
DS39637D-page 86
© 2009 Microchip Technology Inc.
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