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PIC18F4580-I/PT 参数 Datasheet PDF下载

PIC18F4580-I/PT图片预览
型号: PIC18F4580-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与ECAN技术, 10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 490 页 / 8912 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2480/2580/4480/4580  
TABLE 6-2:  
REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)  
Value on Detailson  
File Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
POR, BOR  
Page:  
FSR2H  
Indirect Data Memory Address Pointer 2 High  
---- xxxx  
xxxx xxxx  
---x xxxx  
56, 96  
56, 96  
56, 94  
FSR2L  
Indirect Data Memory Address Pointer 2 Low Byte  
STATUS  
TMR0H  
TMR0L  
N
OV  
Z
DC  
C
Timer0 Register High Byte  
Timer0 Register Low Byte  
0000 0000 56, 153  
xxxx xxxx 56, 153  
1111 1111 56, 153  
T0CON  
TMR0ON  
IDLEN  
T08BIT  
IRCF2  
T0CS  
IRCF1  
IRVST  
T0SE  
IRCF0  
HLVDEN  
PSA  
OSTS  
HLVDL3  
T0PS2  
IOFS  
T0PS1  
SCS1  
HLVDL1  
T0PS0  
SCS0  
OSCCON  
HLVDCON  
WDTCON  
0000 q000  
0-00 0101 56, 273  
--- ---0 56, 359  
36, 56  
VDIRMAG  
HLVDL2  
HLVDL0  
SWDTEN  
RCON  
IPEN  
SBOREN(2)  
RI  
TO  
PD  
POR  
BOR  
0q-1 11q0 56, 133  
xxxx xxxx 56, 159  
0000 0000 56, 159  
0000 0000 56, 155  
1111 1111 56, 162  
-000 0000 56, 159  
TMR1H  
TMR1L  
T1CON  
Timer1 Register High Byte  
Timer1 Register Low Byte  
RD16  
Timer2 Register  
Timer2 Period Register  
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0  
MSSP Receive Buffer/Transmit Register  
MSSP Address Register in I2C Slave Mode. MSSP Baud Rate Reload Register in I2C Master Mode.  
T1RUN  
T1CKPS1  
T1CKPS0  
T1OSCEN  
T1SYNC  
TMR1CS  
TMR1ON  
TMR2  
PR2  
T2CON  
SSPBUF  
SSPADD  
TMR2ON  
T2CKPS1  
T2CKPS0 -000 0000 56, 161  
xxxx xxxx 56, 199  
0000 0000 56, 199  
SSPSTAT  
SSPCON1  
SSPCON2  
ADRESH  
ADRESL  
ADCON0  
ADCON1  
ADCON2  
CCPR1H  
CCPR1L  
CCP1CON  
SMP  
WCOL  
GCEN  
CKE  
D/A  
P
S
R/W  
SSPM2  
PEN  
UA  
BF  
0000 0000 56, 201  
0000 0000 56, 202  
0000 0000 56, 203  
xxxx xxxx 56, 262  
xxxx xxxx 56, 262  
--00 0000 56, 253  
--00 0qqq 56, 254  
0-00 0000 57, 255  
xxxx xxxx 57, 172  
xxxx xxxx 57, 172  
--00 0000 57, 167  
xxxx xxxx 57, 171  
xxxx xxxx 57, 171  
SSPOV  
ACKSTAT  
SSPEN  
ACKDT  
CKP  
SSPM3  
RCEN  
SSPM1  
RSEN  
SSPM0  
SEN  
ACKEN  
A/D Result Register High Byte  
A/D Result Register Low Byte  
CHS3  
VCFG1  
ACQT2  
CHS2  
VCFG0  
ACQT1  
CHS1  
PCFG3  
ACQT0  
CHS0  
PCFG2  
ADCS2  
GO/DONE  
PCFG1  
ADON  
PCFG0  
ADCS0  
ADFM  
ADCS1  
Capture/Compare/PWM Register 1 High Byte  
Capture/Compare/PWM Register 1 Low Byte  
DC1B1  
DC1B0  
CCP1M3  
CCP1M2  
CCP1M1  
CCP1M0  
ECCPR1H(9) Enhanced Capture/Compare/PWM Register 1 High Byte  
ECCPR1L(9)  
Enhanced Capture/Compare/PWM Register 1 Low Byte  
ECCP1CON(9) EPWM1M1 EPWM1M0  
EDC1B1  
PDC5(3)  
EDC1B0  
SCKP  
PDC4(3)  
ECCP1M3  
BRG16  
PDC3(3)  
PSSAC1  
CVR3  
ECCP1M2  
PDC2(3)  
PSSAC0  
CVR2  
ECCP1M1  
WUE  
PDC1(3)  
PSSBD1(3)  
CVR1  
ECCP1M0 0000 0000 57, 172  
BAUDCON  
ECCP1DEL(9)  
ECCP1AS(9)  
CVRCON(9)  
CMCON(9)  
TMR3H  
ABDOVF  
PRSEN  
RCIDL  
PDC6(3)  
ABDEN  
PDC0(3)  
01-0 0000 57, 234  
0000 0000 57, 187  
ECCPASE  
CVREN  
ECCPAS2 ECCPAS1 ECCPAS0  
PSSBD0(3) 0000 0000 57, 187  
CVROE  
C1OUT  
CVRR  
C2INV  
CVRSS  
C1INV  
CVR0  
CM0  
0000 0000 57, 269  
0000 0000 57, 263  
xxxx xxxx 57, 165  
xxxx xxxx 57, 165  
0000 0000 57, 165  
C2OUT  
CIS  
CM2  
CM1  
Timer3 Register High Byte  
Timer3 Register Low Byte  
TMR3L  
T3CON  
RD16  
T3ECCP1(9) T3CKPS1  
T3CKPS0  
T3CCP1(9)  
T3SYNC  
TMR3CS  
TMR3ON  
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition  
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.  
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.  
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices;  
individual unimplemented bits should be interpreted as ‘—’.  
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in INTOSC  
Modes”.  
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.  
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When  
disabled, these bits read as ‘0’.  
7: CAN bits have multiple functions depending on the selected mode of the CAN module.  
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.  
9: These registers are available on PIC18F4X80 devices only.  
DS39637D-page 84  
© 2009 Microchip Technology Inc.  
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