PIC18F2480/2580/4480/4580
TABLE 6-2:
REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
Value on Detailson
POR, BOR Page:
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
B0D7(8)
B0D6(8)
B0D5(8)
B0D4(8)
B0D3(8)
B0D2(8)
B0D1(8)
B0D0(8)
B0D77
B0D67
B0D57
B0D47
B0D37
B0D27
B0D17
B0D07
—
B0D76
B0D66
B0D56
B0D46
B0D36
B0D26
B0D16
B0D06
RXRTR
B0D75
B0D65
B0D55
B0D45
B0D35
B0D25
B0D15
B0D05
RB1
B0D74
B0D64
B0D54
B0D44
B0D34
B0D24
B0D14
B0D04
RB0
B0D73
B0D63
B0D53
B0D43
B0D33
B0D23
B0D13
B0D03
DLC3
B0D72
B0D62
B0D52
B0D42
B0D32
B0D22
B0D12
B0D02
DLC2
B0D71
B0D61
B0D51
B0D41
B0D31
B0D21
B0D11
B0D01
DLC1
B0D70
B0D60
B0D50
B0D40
B0D30
B0D20
B0D10
B0D00
DLC0
xxxx xxxx 64, 305
xxxx xxxx 64, 305
xxxx xxxx 64, 305
xxxx xxxx 64, 305
xxxx xxxx 64, 305
xxxx xxxx 64, 305
xxxx xxxx 64, 305
xxxx xxxx 64, 305
-xxx xxxx 64, 307
B0DLC(8)
Receive mode
B0DLC(8)
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
-x-- xxxx 64, 307
Transmit mode
B0EIDL(8)
B0EIDH(8)
B0SIDL(8)
EID7
EID15
SID2
EID6
EID14
SID1
EID5
EID13
SID0
EID4
EID12
SRR
EID3
EID11
EXID
EID2
EID10
—
EID1
EID9
EID0
EID8
xxxx xxxx 65, 305
xxxx xxxx 65, 304
xxxx x-xx 65, 303
EID17
EID16
Receive mode
B0SIDL(8)
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
xxx- x-xx 65, 303
Transmit mode
B0SIDH(8)
B0CON(8)
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx 65, 302
0000 0000 64, 301
RXFUL
RXM1
RXRTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
Receive mode
B0CON(8)
TXBIF
TXABT
TXLARB
TXERR
TXREQ
RTREN
TXPRI1
TXPRI0
0000 0000 64, 301
Transmit mode
TXBIE
—
—
—
TXB2IE
B2IE
TXB1IE
B1IE
TXB0IE
B0IE
—
—
---0 00-- 65, 324
0000 0000 65, 324
0000 00-- 65, 307
0000 0000 65, 316
0000 0000 65, 315
0000 0101 65, 314
0101 0000 65, 313
0000 0000 65, 312
0000 0000 65, 312
0000 0000 65, 312
0000 0000 65, 312
0000 0000 65, 312
0001 0001 65, 312
0001 0001 65, 312
0000 0000 65, 312
---0 0000 65, 312
0000 0000 65, 311
0000 0000 65, 311
xxxx xxxx 65, 309
BIE0
B5IE
B4IE
B3IE
RXB1IE
—
RXB0IE
—
BSEL0
B5TXEN
FIL15_1
FIL11_1
FIL7_1
FIL3_1
F15BP_3
F13BP_3
F11BP_3
F9BP_3
F7BP_3
F5BP_3
F3BP_3
F1BP_3
—
B4TXEN
FIL15_0
FIL11_0
FIL7_0
FIL3_0
F15BP_2
F13BP_2
F11BP_2
F9BP_2
F7BP_2
F5BP_2
F3BP_2
F1BP_2
—
B3TXEN
FIL14_1
FIL10_1
FIL6_1
FIL2_1
F15BP_1
F13BP_1
F11BP_1
F9BP_1
F7BP_1
F5BP_1
F3BP_1
F1BP_1
—
B2TXEN
FIL14_0
FIL10_0
FIL6_0
B1TXEN
FIL13_1
FIL9_1
B0TXEN
FIL13_0
FIL9_0
MSEL3
FIL12_1
FIL8_1
FIL4_1
FIL0_1
F14BP_1
F12BP_1
F10BP_1
F8BP_1
F6BP_1
F4BP_1
F2BP_1
F0BP_1
FLC1
FIL12_0
FIL8_0
FIL4_0
FIL0_0
F14BP_0
F12BP_0
F10BP_0
F8BP_0
F6BP_0
F4BP_0
F2BP_0
F0BP_0
FLC0
MSEL2
MSEL1
FIL5_1
FIL5_0
MSEL0
FIL2_0
FIL1_1
FIL1_0
RXFBCON7
RXFBCON6
RXFBCON5
RXFBCON4
RXFBCON3
RXFBCON2
RXFBCON1
RXFBCON0
SDFLC
F15BP_0
F13BP_0
F11BP_0
F9BP_0
F7BP_0
F5BP_0
F3BP_0
F1BP_0
FLC4
F14BP_3
F12BP_3
F10BP_3
F8BP_3
F6BP_3
F4BP_3
F2BP_3
F0BP_3
FLC3
F14BP_2
F12BP_2
F10BP_2
F8BP_2
F6BP_2
F4BP_2
F2BP_2
F0BP_2
FLC2
RXFCON1
RXFCON0
RXF15EIDL
RXF15EN
RXF7EN
EID7
RXF14EN
RXF6EN
EID6
RXF13EN RXF12EN
RXF11EN
RXF3EN
EID3
RXF10EN
RXF2EN
EID2
RXF9EN
RXF1EN
EID1
RXF8EN
RXF0EN
EID0
RXF5EN
EID5
RXF4EN
EID4
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices;
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.
DS39637D-page 92
© 2009 Microchip Technology Inc.
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