PIC18F2480/2580/4480/4580
TABLE 6-2:
REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
Value on Detailson
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
Page:
RXF3SIDH
RXF2EIDL
RXF2EIDH
RXF2SIDL
RXF2SIDH
RXF1EIDL
RXF1EIDH
RXF1SIDL
RXF1SIDH
RXF0EIDL
RXF0EIDH
RXF0SIDL
RXF0SIDH
B5D7(8)
B5D6(8)
B5D5(8)
B5D4(8)
B5D3(8)
B5D2(8)
B5D1(8)
B5D0(8)
B5DLC(8)
SID10
EID7
SID9
EID6
SID8
EID5
SID7
EID4
EID12
—
SID6
EID3
SID5
EID2
SID4
EID1
SID3
EID0
xxxx xxxx 62, 308
xxxx xxxx 62, 309
xxxx xxxx 62, 309
xxx- x-xx 62, 308
xxxx xxxx 62, 308
xxxx xxxx 62, 309
xxxx xxxx 62, 309
xxx- x-xx 62, 308
xxxx xxxx 62, 308
xxxx xxxx 62, 309
xxxx xxxx 62, 309
xxx- x-xx 62, 308
xxxx xxxx 62, 308
xxxx xxxx 62, 305
xxxx xxxx 62, 305
xxxx xxxx 62, 305
xxxx xxxx 62, 305
xxxx xxxx 62, 305
xxxx xxxx 62, 305
xxxx xxxx 62, 305
xxxx xxxx 62, 305
-xxx xxxx 62, 307
EID15
SID2
EID14
SID1
EID13
SID0
EID11
EXIDEN
SID6
EID10
—
EID9
EID8
EID17
SID4
EID16
SID3
SID10
EID7
SID9
SID8
SID7
EID4
EID12
—
SID5
EID6
EID5
EID3
EID2
EID1
EID0
EID15
SID2
EID14
SID1
EID13
SID0
EID11
EXIDEN
SID6
EID10
—
EID9
EID8
EID17
SID4
EID16
SID3
SID10
EID7
SID9
SID8
SID7
EID4
EID12
—
SID5
EID6
EID5
EID3
EID2
EID1
EID0
EID15
SID2
EID14
SID1
EID13
SID0
EID11
EXIDEN
SID6
EID10
—
EID9
EID8
EID17
SID4
EID16
SID3
SID10
B5D77
B5D67
B5D57
B5D47
B5D37
B5D27
B5D17
B5D07
—
SID9
SID8
SID7
B5D74
B5D64
B5D54
B5D44
B5D34
B5D24
B5D14
B5D04
RB0
SID5
B5D76
B5D66
B5D56
B5D46
B5D36
B5D26
B5D16
B5D06
RXRTR
B5D75
B5D65
B5D55
B5D45
B5D35
B5D25
B5D15
B5D05
RB1
B5D73
B5D63
B5D53
B5D43
B5D33
B5D23
B5D13
B5D03
DLC3
B5D72
B5D62
B5D52
B5D42
B5D32
B5D22
B5D12
B5D02
DLC2
B5D71
B5D61
B5D51
B5D41
B5D31
B5D21
B5D11
B5D01
DLC1
B5D70
B5D60
B5D50
B5D40
B5D30
B5D20
B5D10
B5D00
DLC0
Receive mode
B5DLC(8)
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
-x-- xxxx 62, 307
Transmit mode
B5EIDL(8)
B5EIDH(8)
B5SIDL(8)
EID7
EID15
SID2
EID6
EID14
SID1
EID5
EID13
SID0
EID4
EID12
SRR
EID3
EID11
EXID
EID2
EID10
—
EID1
EID9
EID0
EID8
xxxx xxxx 62, 305
xxxx xxxx 62, 304
xxxx x-xx 62, 303
EID17
EID16
Receive mode
B5SIDL(8)
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
xxx- x-xx 62, 303
Transmit mode
B5SIDH(8)
B5CON(8)
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx x-xx 62, 302
0000 0000 62, 301
RXFUL
RXM1
RXRTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
Receive mode
B5CON(8)
TXBIF
TXABT
TXLARB
TXERR
TXREQ
RTREN
TXPRI1
TXPRI0
0000 0000 62, 301
Transmit mode
B4D7(8)
B4D6(8)
B4D5(8)
B4D4(8)
B4D3(8)
B4D77
B4D67
B4D57
B4D47
B4D37
B4D76
B4D66
B4D56
B4D46
B4D36
B4D75
B4D65
B4D55
B4D45
B4D35
B4D74
B4D64
B4D54
B4D44
B4D34
B4D73
B4D63
B4D53
B4D43
B4D33
B4D72
B4D62
B4D52
B4D42
B4D32
B4D71
B4D61
B4D51
B4D41
B4D31
B4D70
B4D60
B4D50
B4D40
B4D30
xxxx xxxx 62, 305
xxxx xxxx 62, 305
xxxx xxxx 62, 305
xxxx xxxx 63, 305
xxxx xxxx 63, 305
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices;
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.
© 2009 Microchip Technology Inc.
DS39637D-page 89
MICROCHIP [ MICROCHIP ]
