PIC18F2480/2580/4480/4580
TABLE 6-2:
REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
Value on Detailson
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
Page:
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
EUSART Baud Rate Generator High Byte
EUSART Baud Rate Generator
EUSART Receive Register
0000 0000 57, 236
0000 0000 57, 236
0000 0000 57, 244
0000 0000 57, 241
0000 0010 57, 243
0000 000x 57, 243
0000 0000 57, 111
0000 0000 57, 111
0000 0000 57, 111
xx-0 x000 57, 111
1111 1111 57, 132
EUSART Transmit Register
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
SENDB
ADDEN
BRGH
FERR
TRMT
OERR
TX9D
RX9D
RCSTA
EEADR
EEDATA
EECON2
EECON1
EEPROM Address Register
EEPROM Data Register
EEPROM Control Register 2 (not a physical register)
EEPGD
IRXIP
CFGS
—
FREE
WRERR
TXB1IP
WREN
WR
RD
IPR3
WAKIP
ERRIP
TXB2IP
TXB0IP
RXB1IP
RXB0IP
Mode 0
TXB1IP(8)
TXB1IF
TXB0IP(8)
TXB0IF
IPR3
Mode 1, 2
IRXIP
IRXIF
IRXIF
IRXIE
IRXIE
WAKIP
WAKIF
WAKIF
WAKIE
WAKIE
ERRIP
ERRIF
ERRIF
ERRIE
ERRIE
TXBnIP
TXB2IF
TXBnIF
TXB2IE
TXBnIE
RXBnIP
RXB1IF
RXBnIF
RXB1IE
RXBnIE
FIFOWMIP 1111 1111 57, 132
RXB0IF 0000 0000 57, 126
FIFOWMIF 0000 0000 57, 126
RXB0IE 0000 0000 57, 129
PIR3
Mode 0
TXB1IF(8)
TXB1IE
TXB0IF(8)
TXB0IE
PIR3
Mode 1, 2
PIE3
Mode 0
TXB1IE(8)
TXB0IE(8)
PIE3
Mode 1, 2
FIFOMWIE 0000 0000 57, 129
IPR2
OSCFIP
OSCFIF
OSCFIE
PSPIP(3)
PSPIF(3)
PSPIE(3)
INTSRC
IBF
CMIP(9)
CMIF(9)
CMIE(9)
ADIP
—
—
EEIP
EEIF
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
TUN3
—
HLVDIP
HLVDIF
HLVDIE
CCP1IP
CCP1IF
CCP1IE
TUN2
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TUN1
ECCP1IP(9) 11-1 1111 57, 131
ECCP1IF(9) 00-0 0000 58, 125
ECCP1IE(9) 00-0 0000 58, 128
PIR2
PIE2
—
EEIE
IPR1
RCIP
RCIF
RCIE
—
TXIP
TMR1IP
TMR1IF
TMR1IE
TUN0
1111 1111 58, 130
0000 0000 58, 124
0000 0000 58, 127
PIR1
ADIF
TXIF
PIE1
ADIE
PLLEN(4)
TXIE
OSCTUNE
TRISE(3)
TRISD(3)
TRISC
TRISB
TRISA
LATE(3)
LATD(3)
LATC
TUN4
PSPMODE
0q-0 0000
33, 58
OBF
IBOV
TRISE2
TRISE1
TRISE0
0000 -111 58, 146
1111 1111 58, 143
1111 1111 58, 141
1111 1111 58, 138
1111 1111 58, 135
---- -xxx 58, 146
xxxx xxxx 58, 143
xxxx xxxx 58, 141
xxxx xxxx 58, 138
xxxx xxxx 58, 135
PORTD Data Direction Register
PORTC Data Direction Register
PORTB Data Direction Register
TRISA7(6)
TRISA6(6) PORTA Data Direction Register
—
—
—
—
—
LATE2
LATE1
LATE0
LATD Output Latch Register
LATC Output Latch Register
LATB Output Latch Register
LATB
LATA
LATA7(6)
LATA6(6) LATA Output Latch Register
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices;
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.
© 2009 Microchip Technology Inc.
DS39637D-page 85
MICROCHIP [ MICROCHIP ]
