PIC18F2450/4450
13.2.1
CCP1 PIN CONFIGURATION
13.1 CCP Module Configuration
In Capture mode, the CCP1 pin should be configured
as an input by setting the corresponding TRIS direction
bit.
The Capture/Compare/PWM module is associated with
a control register (generically, CCP1CON) and a data
register (CCPR1). The data register, in turn, is
comprised of two 8-bit registers: CCPR1L (low byte)
and CCPR1H (high byte). All registers are both
readable and writable.
Note:
If RC2/CCP1 is configured as an output, a
write to the port can cause a capture
condition.
13.1.1
CCP MODULE AND TIMER
RESOURCES
13.2.2
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP1IE interrupt enable bit clear to avoid false
interrupts. The interrupt flag bit, CCP1IF, should also
be cleared following any such change in operating
mode.
The CCP module utilizes Timer1 or Timer2, depending
on the mode selected. Timer1 is available to the mod-
ule in Capture or Compare modes, while Timer2 is
available for modules in PWM mode.
TABLE 13-1: CCP MODE – TIMER
RESOURCE
13.2.3
CCP PRESCALER
There are four prescaler settings in Capture mode.
They are specified as part of the operating mode
selected by the mode select bits (CCP1M3:CCP1M0).
Whenever the CCP module is turned off or Capture
mode is disabled, the prescaler counter is cleared. This
means that any Reset will clear the prescaler counter.
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
In Timer1 in Asynchronous Counter mode, the capture
operation will not work.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
13.2 Capture Mode
a
non-zero prescaler. Example 13-1 shows the
In Capture mode, the CCPR1H:CCPR1L register pair
captures the 16-bit value of the TMR1 register when an
event occurs on the corresponding CCP1 pin. An event
is defined as one of the following:
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 13-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
(CCP1 SHOWN)
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
CLRF
CCP1CON
; Turn CCP module off
; Load WREG with the
; new prescaler mode
; value and CCP ON
; Load CCP1CON with
; this value
MOVLW NEW_CAPT_PS
The event is selected by the mode select bits,
CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture
is made, the interrupt request flag bit, CCP1IF, is set; it
must be cleared in software. If another capture occurs
before the value in register CCPR1 is read, the old
captured value is overwritten by the new captured value.
MOVWF CCP1CON
FIGURE 13-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set CCP1IF
CCP1 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
CCPR1H
CCPR1L
TMR1L
TMR1
Enable
TMR1H
4
CCP1CON<3:0>
Q1:Q4
4
DS39760A-page 124
Advance Information
© 2006 Microchip Technology Inc.
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