PIC18F2450/4450
13.4.1
PWM PERIOD
13.4 PWM Mode
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
In Pulse-Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output.
Figure 13-3 shows a simplified block diagram of the
CCP module in PWM mode.
EQUATION 13-1:
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 13.4.3
“Setup for PWM Operation”.
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period].
FIGURE 13-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
CCP1CON<5:4>
Duty Cycle Registers
• TMR2 is cleared
CCPR1L
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
CCPR1H (Slave)
Comparator
Note:
The Timer2 postscalers (see Section 12.0
“Timer2 Module”) are not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
Q
R
S
CCP1
Output
(Note 1)
TMR2
Corresponding
TRIS bit
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
13.4.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> bits contain
the two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
Note 1: The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create
the 10-bit time base.
A PWM output (Figure 13-4) has a time base (period)
and a time that the output stays high (duty cycle).
The frequency of the PWM is the inverse of the
period (1/period).
EQUATION 13-2:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
FIGURE 13-4:
PWM OUTPUT
Period
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 127
MICROCHIP [ MICROCHIP ]
